GS Z80 Max Board

Following is a snippet of Grants design used for this GS Z80 Board. For more information about original design see Grants website.

Snippet of original GS design ...

Specification

8K ROM

56K RAM (A version with 32K RAM is HERE)

Z80 Processor (overclocked - all processors 4MHz+ (Z80B) that I have tried overclock to this with no issues) with a 7.3728MHz clock. You can halve this, ie. to stop the overclocking, by changing the crystal to 3.6864MHz but the serial I/O speed is then also halved to 57600 baud.

115200 Baud serial interface, RS232 specification voltage levels. Full interrupt driven input with buffer and hardware handshaking so no incoming data loss.

Power consumption - approx 200mA

Microsoft BASIC, as used in the Nascom 2 computer modified for the SBC with all I/O via serial. Commands not applicable for the SBC have been removed.

Minimal possible component count - 7 ICs and a small number of discrete components.

Easily interfaced to a large number of connections by adding input ports or output ports and a very small amount of logic.

Memory Map

0000-1FFF   8K ROM

2000-FFFF   RAM (56K) (32K RAM modifications HERE)

I/O Map

00-7F   Free (128 input and 128 output ports)

80-81   SERIAL INTERFACE (minimally decoded, actually covers locations 80 to BF)

C0-FF  Free (64 input and 64 output ports)

Circuit diagram

(Note: Circuit and other details for the 32K RAM version is HERE)

The purpose of this computer is to create the simplest possible machine with a high speed interface, good amount of RAM and also a good implementation of BASIC.

The design that I produced is shown here, and is probably the simplest Z80 circuit that can be done to fulfil what I need. This can be used as the basis of more complex machines.

The ACIA is very minimally decoded but still leaves an I/O address space of 192 free input ports and 192 free output ports (ie. 1536 input bits plus 1536 output bits) available so would be more than adequate. If a more refined decoding is needed then it is straightforward to add additional gates or a 74LS138 decoder. However, even with this simple arrangement, there are many I/O addresses free for expansion.

Note: Chip selection - All of the standard Z80 and 6850 chips that I have worked perfectly at the speeds required for this circuit even though the circuit requirement is faster than their specification. Therefore, you are unlikely to have any issues. However, I would recommend you buy the "B" speed grade ACIA ie. 68B50 and get the 6MHz or 8MHz version of the Z80 processor.

Power supply pins and any (optional) decoupling capacitors are not shown and need to be connected to the appropriate power rails.

Following is the modified design using nvRAM, Gal and peripheral chip (8255)

Fully populated board

Here is the zip file containing the ROM.HEX file that needs to be programmed on the nvRAM chip from address H000 with BASIC starting from H0100. For further info see Grants website.

Note  that in prototype built board I had issues with CPU's running faster than 4MHz ... so in the end I used a 3.686Mhz oscillator. Hence the baud rate for serial is 56K instead of 115K.

GAL code

Name            GS Z80 board,Nascom Basic;

Partno          0001;

Revision        Ver 1;

Date            6/2/18;

Designer        mc;

Company         mcoz;

Location        oz;

Assembly        manual;

Device          g22v10;

/** Inputs **/

pin [1..5] = [a2..6] ;

pin [7..11] = [a7..11] ;

pin [13..16] = [a12..15] ;

pin 18 = nMREQ;

pin 17 = nIOREQ;

pin 19 = nM1;

pin 20 = nRD;

/** Outputs **/

pin 23 = !ramCE;

pin 22 = !pioCS;

pin 21 = !aciaCS;

/** Declarations and Intermediate Variable Definitions **/

field ioaddr= [a15..2];

aciaCS_eqn    = ioaddr:[0080..008F];  

pioCS_eqn   = ioaddr:[00C0..00FF];

ramCE_eqn    = ((ioaddr:[0000..1FFF])& !nRD)#(ioaddr:[2000..FFFF]);

/** Logic Equations **/

pioCS = pioCS_eqn & !nIOREQ;

aciaCS  = aciaCS_eqn & !nIOREQ;

ramCE  = ramCE_eqn & !nMREQ;

Basic operational functions of Z80 microprocessor