Embedded Files
This design of 6802 based board follows from the original design of MOTOROLA MEK6800D2 development board back in late 1970's.
The design is not an exact replica ..but functionally representative of the original board. In fact it is way more flexible than the original board.
The board implements a 6802 processor instead of 6800. Also to save on lots of "GLUE" logic chips, a CPLD is used to simplify the circuit and also chip count. The whole board is on one PCB with a keypad.
Some of the features of this design are:
Functionally equivalent to original D2 Kit
Can be reprogrammed and used with lots of other MONITOR type programs
Easy CPLD programming via JTAG connector
NRAM use- can be used as RAM or ROM .. also keeps data once power is off
Larger LED display
Extra ACIA for comms port (has 2 comm ports) .. can run @115K baud
Extra PIA chip for extra ports
Disconnecting Keypad/LED section allows extra PIA port access
Following is the board and display schematic ..
Please note the above schematics should be correct .. as the prototype PCB had few errors. First note that the "RME "keys are in different order then the original keypad. However they work as expected . This can be corrected if needed by looking at original D2 keypad design.. although unnecessary. In next version of PCB that will be corrected.
Second one is that the DATA LED digits have been reversed in wiring ..so see mod below on back of pcb .. best done with no components..
Cut tracks in 3 spots (RED). Make 3 joins once components are in (YELLOW).
Programming CPLD and NVRAM
In this setup to make the board run the JBUG Monitor .. The MONITOR software is programmed in memory locations
E000-EFFF and FC00-FFFF using a typical universal programmer which is able to program NVRAM DS1245Y chips such as ones from Wellon.
The CPLD chip (EPM7128SLC84) can be programmed using ALTERA USB Blaster programmer. They are reasonably cheap on Ebay.
Program CPLD with no major chips present on board ... using JTAG connector socket and Quartus 13.0sp1 software program.
The major function of the CPLD chip is as follows:
Provide clock divides from master clock for the ACIA clocks
ABSOLUTE address decoding for all memory mapped chips down to byte level
Decode Read and Write signal lines for RAM
Possible ROM - not implemented in this option ... ROM is programmed in NVRAM
Few other comments about the board ..power consumption with all chips present is just about 0.5A ...
Following shows comms connection to TTL to USB converter. Also see link J4 which grounds the A16 pin of the unused half of the NVRAM. That link can be changed to +5V if you want to have different versions of code in 2 half's of NVRAM.
Memory MAP
0000-3FFF user RAM
800-8007 2nd PIA
8008-800F ACIA (Tape)
8010-801F 2nd ACIA
8020-8004 PIA (keypad)
A000-A0FF System RAM
E000-EFFF JBUG
FC00-FFFF JBUG copy for RESET vectors
Following is the VHDL code for the CPLD. There is enough comments to be able to understand what the code is doing.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpldD2 is
Port ( vma : in std_logic;
rnw : in std_logic;
nreset : in std_logic;
nrd : out std_logic;
nwr : out std_logic;
address : in std_logic_vector(15 downto 0);
csbar : out std_logic_vector(4 downto 0);
clockIn : in STD_LOGIC; -- MClock pin 70 (3.6Mhz)
Data_out : inout std_logic_vector(7 downto 0);
clockout2 : out STD_LOGIC; -- divided MClock/2 -->1.8MHz
clockout4 : out STD_LOGIC);-- divided MClock/4 clock -->0.9MHz
end cpldD2;
architecture Behavioral of cpldD2 is
signal clockTemp : std_logic_vector (2 downto 0);
begin
-- clock divider
process (clockIn)
begin
if (clockIn'Event and clockIn = '1') then
clockTemp <= clockTemp + '1';
end if;
end process;
clockout2 <= clockTemp(0); -- divided by 2 clock
clockout4 <= clockTemp(1); -- divided by 4 clock
-- set D0-D7 @ high Impedance TRISTATE
Data_out <= "ZZZZZZZZ";
-- CS NVRAM 0000-03FFF,A000-A0FF as RAM E000-EFFF,FC00-FFFF as ROM
csbar(0) <= '0' when
((vma = '1') and (rnw ='1') and (nreset= '1') and
(((address >= X"E000") and (address <= X"E3FF")) or ((address >= X"FC00") and (address <= X"FFFF"))))
or
((vma = '1') and (nreset= '1') and
((address >= X"0000") and (address <= X"3FFF")))
or
((vma = '1') and (nreset= '1') and
((address >= X"A000") and (address <= X"A0FF")))
else '1';
-- CS ACIA TAPE 8008-800F
csbar(1) <= '0' when
((vma = '1')and (nreset= '1') and
((address >= X"8008") and (address <= X"800F")))
else '1';
-- CS 2nd ACIA 8010-801F
csbar(2) <= '0' when
((vma = '1') and (nreset= '1') and
((address >= X"8010") and (address <= X"801F")))
else '1';
-- Keypad PIA 8020-8024
csbar(3) <= '0' when
((vma = '1') and (nreset= '1') and
((address >= X"8020") and (address <= X"8024")))
else '1';
-- 2nd PIA 8000-8007
csbar(4) <= '0' when
((vma = '1') and (nreset= '1') and
((address >= X"8000") and (address <= X"8007")))
else '1';
-- Seperate NREAD and NWRITE signals from rnw
nrd <= not (rnw and vma);
nwr <= not((not(rnw)) and vma);
end Behavioral;
PIN Assignment File for CPLD
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 22:28:00 August 05, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# cpldD2_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY cpldD2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:28:00 AUGUST 05, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VHDL_FILE cpldD2.vhd
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_70 -to clockIn
set_location_assignment PIN_65 -to clockout2
set_location_assignment PIN_68 -to clockout4
set_location_assignment PIN_73 -to Data_out[7]
set_location_assignment PIN_74 -to Data_out[6]
set_location_assignment PIN_75 -to Data_out[5]
set_location_assignment PIN_76 -to Data_out[4]
set_location_assignment PIN_77 -to Data_out[3]
set_location_assignment PIN_79 -to Data_out[2]
set_location_assignment PIN_80 -to Data_out[1]
set_location_assignment PIN_81 -to Data_out[0]
set_location_assignment PIN_12 -to rnw
set_location_assignment PIN_4 -to vma
set_location_assignment PIN_56 -to csbar[0]
set_location_assignment PIN_54 -to csbar[1]
set_location_assignment PIN_55 -to csbar[2]
set_location_assignment PIN_50 -to address[15]
set_location_assignment PIN_48 -to address[14]
set_location_assignment PIN_46 -to address[13]
set_location_assignment PIN_44 -to address[12]
set_location_assignment PIN_40 -to address[11]
set_location_assignment PIN_37 -to address[10]
set_location_assignment PIN_35 -to address[9]
set_location_assignment PIN_33 -to address[8]
set_location_assignment PIN_31 -to address[7]
set_location_assignment PIN_29 -to address[6]
set_location_assignment PIN_27 -to address[5]
set_location_assignment PIN_24 -to address[4]
set_location_assignment PIN_22 -to address[3]
set_location_assignment PIN_20 -to address[2]
set_location_assignment PIN_17 -to address[1]
set_location_assignment PIN_15 -to address[0]
set_location_assignment PIN_61 -to csbar[4]
set_location_assignment PIN_58 -to csbar[3]
set_location_assignment PIN_52 -to nreset
set_location_assignment PIN_10 -to nrd
set_location_assignment PIN_8 -to nwr
set_global_assignment -name CDF_FILE output_files/Chain4.cdf
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
If you cannot be bothered with Quartus software .. and just want to program the CPLD with ready made code for JBUG monitor? .. then you can just use the Quartus II Programmer - download the software and program the POF file below..
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