68Kb Board

This is updated version of 68000NV board. This board has extra features like:

• • 2 GAL chips for extra decoding

  • An extra UART 68B50, to cater for designs that use this UART for comms

  • 74LS164 chip to take care of low address RESET startup vectoring

  • Using GAL chip to provide 1.8MHz clock

The design of the board is as following picture ..

See video below for more detailed explanation of the workings of the board ...

And image of the BLANK PCB Board (top)

See video below for better explanation of the PCB components and their function...

On constructing the board ..some resistors have to be mounted under the 64 pin IC socket. Depending on the type of socket you have ..this might be different in assembly ...

Completed board ...  short out links  V and A   .. and R  and H

Add extra ~LDS line to GAL1 chip (pin 18)  ... from GAL2 chip  ....(pin3).

Programming the 2 gal chips   ...code ...

Gal 1 Code

Name            68K ram/rom;

Partno          0001;

Revision        68Kb G1;

Date            21/9/18;

Designer        mc;

Company         mcoz;

Location        oz;

Assembly        manual;

Device          g22v10;

/** Inputs **/

Pin 1 = nas;

pin 2 = rnw;

pin 3 = sio_ndtack;

pin 4 = rmem;

pin 5 = a23;

pin 6 = a22;

pin 7 = a21;

pin 8 = a20;

pin 9 = a19;

pin 10 = a18;

pin 11 = a17;

pin 13 = a16;

pin 14 = a15;

pin 15 = a14;

pin 16 = a13;

pin 17 = a12;

pin 18 = nlds;

/** Outputs **/

pin 23 = !cs_sio;

pin 22 = !cs_ram;

pin 21 = !dtack;

pin 20 = rom;

pin 19 = !cs_68b50;

/** Declarations and Intermediate Variable Definitions **/

field ioaddr= [a12..23];

cs_ram_eqn   = ((ioaddr:[000000..003FFF])& rnw & !nas ) # ((ioaddr:[004000..00BFFF])& !nas) ;

cs_sio_eqn   = (ioaddr:[00C000..00CFFF])&!nas & !nlds;

/** Logic Equations **/

cs_ram = cs_ram_eqn;

cs_sio = cs_sio_eqn;

rom = a19;

dtack = !nas;

GAL 2 code

Name            68K ram/rom;

Partno          0001;

Revision        68Kb Gal 2;

Date            20/9/18;

Designer        mc;

Company         mcoz;

Location        oz;

Assembly        manual;

Device          g22v10;

/** Inputs **/

pin 1 = clk36;

pin 2 = rnw;

pin 3 = nlds;

pin 4 = nuds;

/** Outputs **/

pin 23 = !lwr;

pin 22 = !lrd;

pin 21 = !uwr;

pin 20 = !urd;

pin 18 = uds;

pin 17 = lds;

/** Declarations and Intermediate Variable Definitions **/

/** Logic Equations **/

lwr = !rnw & !nlds;

lrd = rnw & !nlds;

uwr = !rnw & !nuds;

urd = rnw & !nuds;

uds = !nuds;

lds = !nlds;

Memory space:

• • Mon ROM     0000-3FFF

  • RAM             4000-BFFF

  • Duart           C000-CFFF

The monitor Binary files:

• MonVer5UR

• MonVer5LR

Programming GAL and NVRam chips.

Following video shows you how to compile and produce jed files to program into GAL chips. Also how to program the upper and lower byte NVram chips for the board ..

And finally here is video of the board running and using the monitor program to run some programs ...