Energy-Efficient Computing Hardware

I focused on efficient interposer-based System-in-Package (SiP) designs to address challenges in integrating multiple heterogeneous dies. Traditional integrated circuit (IC) integration can limit performance, while large system-on-chips (SoCs) are costly and complex. As SiP interposer complexity increases with multiple heterogeneous dies, I developed an automated I/O library generation flow that designs all-digital I/O circuits tailored to specific wire trace characteristics, enhancing system delay and energy efficiency. This flow produces standard cells with complete layouts, seamlessly integrating into the physical design process. Demonstrated on various SiP designs using advanced CMOS and BEOL technologies, this approach improves communication efficiency and design simplicity, supporting high-performance, low-cost SiP solutions. This work was recognized in S3S’18 (Best Student Paper nominated), EPEPS’18 (Best Student Paper nominated) and TCPMT’19. This work was funded by DARPA CHIPS Program.