Research

FerroElectronics

Data storage is the foundation of any information processing system. Most computing systems follow a von Neumann architecture, meaning the central processing unit (CPU) and the memory unit are separate entities. Instruction execution by the CPU and data modification in the memory system are separate operations and cannot co-occur. CPU’s processing speed is typically much faster than memory throughput, leading to a bottleneck called the ‘memory wall.’ As the shift in market trends imposes a growing number of data-centric applications, developing faster devices to perform the memory task becomes imperative. So far, complementary metal-oxide semiconductors (CMOS) based memories like SRAM, DRAM, and Flash memory have fulfilled the memory segment. Still, exciting alternative technologies have emerged lately, including novel non-volatile memory (NVM) cell types. Among them, hafnium oxide-based ferroelectric memories constitute a strong candidate for ensuring fast write speed, low power, and high endurance. Our group focuses on developing ferroelectric memories from atomic-level investigation to higher-level applications. Understanding that the research from material to system should be synchronized for actual development is essential. A small change in doping concentration or crystal structure can create havoc in the system-level applications. Our group focuses on connecting the four islands of material, device, circuit, and system.

Making "Mind" with semiconductors

The introduction of neural networks (NN), particularly the convolution neural network, ushered in a new era of computing, with machine learning emerging as the preferred method for handling a wide range of problems. However, the software-based artificial neural networks (ANN) used in traditional von Neumann computing systems experience severe bottlenecks due to the delay caused by data transmission between segregated memory units and processor units. This bottleneck has grown increasingly apparent with the proliferation of edge devices in recent years. Their real-time data demonstrated the need to overcome data transfer latency and energy costs between the processor unit and memory in von Neumann's architecture. Our group focuses on designing and taping chips with emerging non-volatile memories for several computing-in-memory, logic-in-memory, and other edge applications.

S. De et al., "Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array," in IEEE Electron Device Letters, doi: 10.1109/LED.2022.3216558.
Raffel.Yannick et al.,. Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications. ACS Applied Electronic Materials, 4(11). https://doi.org/10.1021/acsaelm.2c00771
S. De et al., "READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications," in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2022.3195119
Rana Sk, M., et al., Ferroelectric Content Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation. ACS Applied Electronic Material.

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