Study and References

[1] Alexandra Stanciu, Marcian N. Cirstea , Senior Member, IEEE,and Florin umitru Moldoveanu “Analysis and Evaluation of PUF-Based SoC Designs for Security Applications”, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL.63,No.9.SEPTEMBER 2016

[2] Filip Kod´ytek and R´obert L´orencz Czech Technical University Department of Computer Systems Prague, Th´akurova 9 “A design of ring oscillator based PUF on FPGA”-2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

[3] Abhranil Maiti, Vikash Gunreddy, and Patrick Schaumont-P. Athanas et al. (eds.) “A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions”, Embedded Systems Design with FPGAs,DOI 10.1007/978-1-4614-1362-2 11, © Springer Science+Business Media, LLC 2013 reference

[4] Florent Bernard, Viktor Fischer, Crina Costea, Robert Fouquet “Implementation of Ring Oscillators Based Physical Unclonable Functions with Independent Bits in the Response” International Journal of Recongurable Computing, Hindawi Publishing Corporation, 2012, 2012 Article ID 168961, 11 p.

[5] Abhranil Maiti and Patrick Schaumont “Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive” Secure Embedded Systems Lab, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA

[6] Xin Xin, Jens-Peter Kaps, Kris Gaj “A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs” Electrical and Computer Engineering Department George Mason University

[7]G. Suh and S. Devadas, “Physical unclonable functions for device authentication and secret key generation” in DAC, Jun. 2007.

[8]Charles Herder, Meng-Day (Mandel) Yu, Farinaz Koushanfar, and Srinivas Devadas “Physical Unclonable Functions and Applications: A Tutorial” This paper is a tutorial on ongoing work in physical-disΔorder-based security,security analysis, and implementation choices

[9] Mehrdad Majzoobiy;1, Farinaz Koushanfary;2, Srinivas Devadasz;3 † “FPGA PUF using Programmable Delay Lines” Electrical and Computer Engineering Department, Rice University 6100 Main Street, Houston, TX 77005 United States

[10] J. Anderson, “A PUF design for secure FPGA-based embedded systems” in ASP-DAC, Jan. 2010, pp. 1–6.

[11] R. Maes and I. Verbauwhede, “Physically unclonable functions: a study on the state of the art and future research directions,” in Towards Hardware-Intrinsic Security, Security and Cryptology, 2010.

[12] R. Pappu, R. Recht, and J. Taylor, “Physical one-way functions,” Science, pp. 2026–2030, Sep. 2002.

[13]Gassend, B., Clarke, D., van Dijk, M., Devadas, S “Silicon physical random functions In: ACM Conference on Computer and Communications Security, pp. 148{160. ACMPress, New York, NY, USA (2002)

[14] Chongyan Gu (QUB), Neil Hanley (QUB), Robert Hesselbarth (AISEC),

Martin Hutle (AISEC), Gavin McWilliams (QUB) “PUF enhanced smart meter hardware architecture and an authentication/key management deployment architecture “ SPARKS, Smart Grid Protection Against CybeR Attacks ,

[15]S. Drimer. Volatile FPGA design security–a survey. IEEE Computer Society Annual Volume, pages 292–297, 2008.

[16]Abhranil Maiti “A Systematic Approach to Design an Efficient Physical Unclonable Function” PhD thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University

[17]Maes R, chapter 2 “Physically Unclonable Functions: Concept and Constructions”Physically unclonable Functions construction , Properties and applications: http://www.springer.com/978-3-642-41394-0

[18]Ulrich Ru¨hrmair, Frank Sehnke, Jan So¨lter, Gideon Dror, Srinivas Devadas, and Ju¨rgen Schmidhuber. Modeling attacks on physical unclonable functions. In Proceedings of the 17th ACM conference on Computer and communications security, CCS ’10, pages 237– 249, New York, NY, USA, 2010. ACM. 1, 2.4, 3.1.2, 3.4.2, 3.5.1

[19]J. Guajardo, S.S. Kumar, G.-J. Schrijen, P. Tuyls, FPGA intrinsic PUFs and their use for IP protection, in Proceedings of the 9th International Workshop on Cryptographic Hardware and Embedded Systems. LNCS, vol. 4727 (2007), pp. 63–80

[20] P. Sedcole, P.Y.K. Cheung,Within-die delay variability in 90-nm FPGAs and beyond, in Proceedings of International Conference on Field Programmable Technology (IEEE, New York, 2006), pp. 97–104

[21] “Xilinx Constraints Guide ” ,“Datasheets for Spartan 3 and 3E Devices”

[22]https://www.fpgarelated.com/showthread/comp.arch.fpga/16946-1.php