Research and Development on FPGA Based PUF circuits

PUF- Physically Unclonable functions

Design Challenges

• Systematic process variation like asymmetry in routing can result in false positives in chip authentication (Bit aliasing)
• Dynamic variation like varying ambient temperature, thermal noise, supply voltage variation
• Delay imbalances are dictated by the placement and routing constraints
• FPGA constraints like maximizing the use of each slice, increasing the number of response bits to number of challenge bits, generating higher CRPs
• To ensure symmetry, manual routing is essential leading to defining Hard Macros
• Hard Macro implementation requires timing, mapping, placement and routing constraints to be considered

1. Design a Strong Physically unclonable function circuit on FPGA based system.

2. Extract Unique challenge Response Pairs (CRPs) from the specified FPGA device.

3. Study the Proposed PUF’s Performance Characteristics (Metrics) that decide the unclonable nature of PUF circuit and analyse how the adjacent digital circuit activity can influence the PUF responses.

4. FPGA Target Devices :

Phase 1: Xilinx Spartan 3 and 3E architecture specific FPGAs (with only PL)

Phase 2: Xilinx Artix7 Architecture Specific FPGAs (with PS and PL)

Phase 3: Xilinx Zync Boards with All programmable SoC System Architecture

5. Implementation of a PUF Node(Smart Meter) ,Host and a Gateway environment (TEST BED) using the above mentioned Target Boards and perform a secure transaction from Host to Node through Gateway.

Publications