Quang Dang Truong, Hien Nguyen, Tuy TanNguyen, and Hanho Lee, "NIST Post-Quantum Cryptography Standards: A Comprehensive Review of Theoretical Foundations and Implementations", IEEE Access, October. 2025. (submitted)
Ardianto Satriawan, Rella Mareta, and Hanho Lee, "A Survey and Review on the BFV Homomorphic Encryption Hardware Architecture Implementations", IEEE Access, October. 2025. (submitted)
Quang Dang Truong, Yunseong Jang, and Hanho Lee, "High-performance Unified Hardware Architecture for ML-DSA and ML-KEM PQC Standards", IEEE Access, October. 2025. (submitted)
Rella Mareta, Ardianto Satriawan, and Hanho Lee, "High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption," IEEE Open Journal of Circuits and Systems, June. 2025. (accepted)
Kyungkyun Kang, Seulbee Yang, Giang Troung Le, and Hanho Lee, "HLS-based Hardware/Software Co-Design of ML-KEM Post-Quantum Cryptosystem for Real-Time Video Encryption", Journal of Semiconductor Technology and Science, vol. 25, no.05, pp.1598-1657, October.2025.
Haesung Jung, Quang Dang Truong, and Hanho Lee, "Highly-Efficient Hardware Architecture for ML-KEM PQC Standard," IEEE Open Journal of Circuits and Systems, pp. 356-369, 22 July. 2025. (DOI:10.1109/OJCAS.2025.3591136)
Quang Dang Truong, Phap Duong-Ngoc, and Hanho Lee, "Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption," IEEE Transactions on Very Large Scale Integration(VLSI) Systems, pp. 2039-2043, July. 2025. (DOI: 10.1109/TVLSI.2025.3552852)
Hanyoung Lee, Ardianto Satriawan, and Hanho Lee, "Homomorphic Evaluation Cluster Architecture for Fully Homomorphic Encryption," IEEE Open Journal of Circuits and Systems, pp. 135-146, 08 May. 2025. (DOI:10.1109/OJCAS.2025.3568058)
Ardianto Satriawan, Rella Mareta, and Hanho Lee, "Integer Modular Multiplication with Barrett Reduction and Its Variants for Homomorphic Encryption Applications: A Comprehensive Review and An Empirical Study," IEEE Access, vol. 12, pp. 147283-147300, October 2024. (DOI:10.1109/ACCESS.2024.3473901)
Hyunseon Kim, Haesung Jung, Ardianto Satriawan, and Hanho Lee, "A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4678-4682, November 2024. (DOI: 10.1109/TCSII.2024.3442228)
Chulwoo Lee, Hanyoung Lee, Ardianto Satriawan, and Hanho Lee,"Configurable Arithmetic Core Architecture for RNS-CKKS Homomorphic Encryption," IEEE Access, vol. 12, pp. 147220-147234, October 2024. (DOI:10.1109/ACCESS.2024.3473903)
Chang-Hyeon Lee, Jae-Hyeok Lee, Haesung Jung, Hanyoung Lee, and Hanho Lee, "HLS-based HW/SW Co-design and Hybrid HLS-RTL Design for Post-Quantum Cryptosystem," Journal of Semiconductor Technology and Science, vol. 24, no. 03, p.191-198, June 2024. (DOI:/10.5573/JSTS.2024.24.3.191)
Rella Mareta, Ardianto Satriawan, Phap Ngoc Duong, and Hanho Lee, “A bootstrapping-capable configurable NTT architecture for fully homomorphic encryption," IEEE Access, vol. 12, pp. 52911-52921, April 10. 2024. (DOI: 10.1109/ACCESS.2024.3386977)
Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmaio Zhang, "Hardware Circuits and Systems Design for Post-Quantum Cryptography – A Tutorial Brief," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 3, pp. 1670-1676, March 2024. (DOI: 10.1109/TCSII.2024.3357836)
Quang Dang Truong, Phap Duong-Ngoc, and Hanho Lee, "Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard," IEEE Access, vol. 12, pp. 32395-32407, Feb. 2024. (DOI: 10.1109/ACCESS.2024.3370470)
Thang Xuan Pham, Phap Duong-Ngoc, and Hanho Lee, "An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 12, pp. 4854-4864, Dec. 2023. (IF 5.1)
Stefanus Kurniawan, Phap Duong-Ngoc,and Hanho Lee, "Configurable Memory-Based NTT Architecture for Homomorphic Encryption," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 70, No. 10, Oct. 2023. (IF 4.4) (ISICAS 2023 Presentation (10/24))
Jaehyeok Lee, Phap Duong-Ngoc, Hanho Lee, "Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption," Sensors, vol. 23, no. 17, 24 Aug. 2023.
Thang Xuan Pham, Tuy Tan Nguyen and Hanho Lee, "Hamming-distance Trellis Min-Max-based Architecture for Non-binary LDPC Decoder" IEEE Transactions on Circuits and Systems II., vol. 70, no. 7, pp. 2390-2394, July 2023. (IF 3.691)
Phap Duong-Ngoc, and Hanho Lee, "Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption." Sensors, vol. 23, no. 10, 9 May. 2023. (IF 3.847)
Phap Duong-Ngoc, Sunmin Kwon, Donghoon Yoo, and Hanho Lee "Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no.3, pp. 1270-1282, March 2023. (IF 5.1)
Tuy Tan Nguyen, Sungjae Kim, Yongjun Eom, and Hanho Lee, "Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber," Applied Sciences, vol. 12, no. 11, pp. 5305, May 2022. (IF 2.679)
Thang Xuan Pham and Hanho Lee, "Efficient First Four Minimum Values Finder for NB-LDPC Decoders with Compressed Messages," IEEE Transactions on Circuits and Systems II, vol. 69, no. 3, pp. 1024-1028, Mar. 2022. (IF 3.292)
Tuy Tan Nguyen, Tram Thi Bao Nguyen, and Hanho Lee, "An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms," Electronics, vol. 11, no. 6, pp. 891, Mar. 2022. (IF 2.397)
Tuy Tan Nguyen, Tram Thi Bao Nguyen, and Hanho Lee, "Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders," Sensors, vol. 22, no. 5, pp. 891, Feb. 2022. (IF 3.847)
Phap Duong Ngoc and Hanho Lee, "Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography," IEEE Access, vol. 10, pp. 12732-12741, Jan. 2022. (IF 3.367)
Tram Thi Bao Nguyen, Tuy Tan Nguyen, and Hanho Lee, "Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication," Electronics, vol. 10, no. 4, pp. 516, Feb. 2021. (IF 2.397)
Thang Xuan Pham, Tuy Tan Nguyen, and Hanho Lee, "Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes," IEEE Transactions on Circuits and Systems II, vol. 68, no. 1, pp. 216-220, Jan. 2021. (IF 2.814)
Phap Duong-Ngoc, Tuy Tan Nguyen, and Hanho Lee, "Efficient NewHope Cryptography Based Facial Security System on a GPU," IEEE Access, vol. 8, no. 1, pp. 108158-108168, Jun. 2020. (IF 3.745)
Tuy Tan Nguyen, Tram Thi Bao Nguyen, and Hanho Lee, "High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components," Electronics, vol. 9, no. 7, pp. 1075, Jun. 2020. (IF 2.412)
Tuy Tan Nguyen, Tram Thi Bao Nguyen, and Hanho Lee, "High-efficiency Low-latency NTT Multiplier Architecture for Ring-LWE Cryptography," Journal of Semiconductor Technology and Science (JSTS), vol. 20, no. 2, pp. 220-223, Apr. 2020. (SCIE)
Huyen Pham Thi, Hanho Lee, and Xuan Nghia Pham, "Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes," Integration, the VLSI Journal, vol. 69, pp. 234-241, Apr. 2019. (IF 1.214)
Tram Thi Bao Nguyen, Tuy Tan Nguyen, and Hanho Lee, "Efficient QC-LDPC Encoder for 5G New Radio," Electronics, vol. 8, no. 6, pp. 668, Jun. 2019. (IF 2.110)
Tram Thi Bao Nguyen and Hanho Lee, "Low-Complexity Multi-Mode Multi-Way Split-Row Layered LDPC Decoder for Gigabit Wireless Communications," Integration, the VLSI Journal, vol. 65, pp. 189-200, Mar. 2019. (IF 1.150)
Tuy Tan Nguyen and Hanho Lee, "Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors," Electronics, vol. 8, no. 4, pp. 413, Apr. 2019. (IF 2.110)
Tuy Tan Nguyen and Hanho Lee, "High-Secure Fingerprint Authentication System using Ring-LWE Cryptography," IEEE Access, vol. 7, no. 1, pp. 23379-23387, Feb. 2019. (IF 4.098)
Taesung Kim, and Hanho Lee, "High-Performance Syndrome-based SD-BCH Decoder Architecture using Hard-Decision Kernel," Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 6, pp. 694-703, Dec. 2018.[PDF] (SCIE)
Seunghun Oh, and Hanho Lee, "High-Performance Parallel Concatenated Polar-CRC Decoder Architecture," Journal of Semiconductor Technology and Science (JSTS), vol. 18, no. 5, pp. 560-567, Oct. 2018.[PDF] (SCIE)
Tuy Tan Nguyen and Hanho Lee, "High-Performance Ring-LWE Cryptography Scheme for Biometric Data Security," IEIE Transactions on Smart Processing and Computing, vol. 7, no. 2, pp. 97-106, Apr. 2018. [PDF] (Scopus)
Huyen Pham Thi, and Hanho Lee, "Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes with High-Order Galois-Fields," IEEE Transactions on VLSI Systems, vol. 26, no. 3, pp. 496-507, Mar. 2018.[PDF] (IF 1.744)
Sabooh Ajaz, Tram Thi Bao Nguyen, and Hanho Lee, "An Area-Efficient Half-Row Pipelined Layered LDPC Decoder Architecture," Journal of Semiconductor Technology and Science (JSTS), pp. 845-853, Dec. 2017.[PDF] (SCIE)
Huyen Pham Thi, Sabooh Ajaz and Hanho Lee, "High-Throughput Partial-Parallel Block-Layered Decoding Architecture for Nonbinary LDPC Codes," Integration, the VLSI Journal, vol. 59, pp. 52-63, Sept. 2017.[PDF] ( IF 0.906, SCIE)
Huyen Pham Thi, and Hanho Lee, "Efficient Parallel Block-Layered Nonbinary LDPC Decoding on a GPU," IEIE Transactions on Smart Processing and Computing, vol. 6, no. 3, pp. 210-219, June 2017. [PDF]
Huyen Pham Thi, and Hanho Lee, "Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes" IEEE Transactions on VLSI Systems, vol. 25, no. 5, pp. 1787-1791, May 2017.[PDF] (IF 1.744)
Tram Thi Bao Nguyen and Hanho Lee, "High-Throughput Low-Complexity Mixed-Radix FFT Processor using a Dual-Path Shared Complex Constant Multiplier," Journal of Semiconductor Technology and Science (JSTS), vol. 17, no. 1, pp. 101-109, Feb. 2017. [PDF] (SCIE)
Boseok Jeong, Taesung Kim, Hanho Lee, "Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications," Journal of Semiconductor and Science Technology (JSTS), vol. 16, no. 4, pp. 488-496, Aug. 2016.[PDF] (SCIE)
Tuy Tan Nguyen and Hanho Lee, "Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor," Journal of Semiconductor Technology and Science (JSTS), vol. 16, no. 1, pp. 118-125, Feb. 2016.[PDF] (SCIE)
Ha-Ram Yun, and Hanho Lee, "Simplified merged processing element for successive-cancellation polar decoder," IET Electronics Letters, Vol. 52, No. 4, pp. 270-272, Feb. 18. 2016.[PDF] (IF 1.155)
Sabooh Ajaz, Hanho Lee, "Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications," Integration, the VLSI Journal, vol. 51, no. 3, pp. 21-36, Sept. 2015.[PDF] (IF 0.703, SCIE)
Cheolho Kim, Haram Yun, Sabooh Ajaz, Hanho Lee, "High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture", Journal of Semiconductor Technology and Science (JSTS), vol.15, no. 3, pp. 427-435, Jun, 2015.[PDF] (SCIE)
Chang-Seok Choi and Hanho Lee, “Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes,” Journal of Signal Processing Systems, vol. 78, no. 2, pp. 209-222, Feb. 2015.[PDF]
Sabooh Ajaz and Hanho Lee, “An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders," IEICE Electronics Express, vol. 11, No. 2, pp. 1-6, Jan. 25, 2014.[PDF] (SCIE)
Jaewoong Yeon, Seung-Jun Yang, Chelho Kim, Hanho Lee, “Low-Complexity Triple-Error-Correcting Parallel BCH Decoder,” Journal of Semiconductor and Science Technology, vol.13, no. 5, pp. 465-472, Oct. 2013.[PDF] (SCIE)
Sabooh Ajaz and Hanho Lee, "Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for gigabit wireless communications," IET Electronics Letters, vol. 49, no. 19, pp. 1246-1248, Sept. 12. 2013.[PDF] (IF 1.068)
Seong-In Hwang, Hanho Lee, “Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design,” IEEE Transactions on VLSI Systems, vol.21, no. 7, pp. 1337-1341, July 2013. [PDF] (IF 1.142)
Taesang Cho and Hanho Lee, “A High-Speed Low-Complexity Modified Radix-2^5 FFT Processor for High-Rate WPAN Applications,” IEEE Transactions on VLSI Systems, Vol. 21, NO. 1, pp. 187-191, Jan 2013. [PDF] (IF 1.142)
Jeong-In Park, and Hanho Lee, “A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol.E95-A, no. 12, pp. 2424-2429, Dec. 1. 2012. [PDF] (SCIE)
Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee, “A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100Gb/s Optical Communications,” Journal of Signal Processing Systems, vol. 6, no. 1, pp. 43-55, Jan. 2012. [PDF]
Kisun Jung, Hanho Lee, “Low-Complexity Multi-Mode Memory-based FFT Processor for DVB-T2 Applications,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems, vol.E94-A, no. 11, pp. 2376-2383, Nov. 2011. [PDF] (SCIE)
Sangmin Kim, Gerald E. Sobelman, and Hanho Lee, "A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes," IEEE Transactions on VLSI Systems, vol. 19, no. 6, pp. 1099-1103, June 2011 [PDF] (IF 1.219)
Chang-Seok Choi, Hyo-Jin Ahn, Hanho Lee, "High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems," IEICE Transactions on Communications, Vol.E94-B,No.05,pp.1332-1338, May 2011. [PDF] (SCIE)
Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, “Low-Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems Vol. E94-A, No. 3, pp. 937-945 , March 2011. [PDF] (SCIE)
Jeong-In Park and Hanho Lee , "Area-Efficient Truncated Berlekamp-Massey Architecture for Reed-Solomon Decoders,” IET Electronics Letters,vol. 47, no. 4, pp. 241-243, Feb. 17, 2011.[PDF] (IF 0.965, SCIE)
Jeong-In Park, Kihoon Lee, Chang-Seok Choi, Hanho Lee, “High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey algorithm and Its Folded Architecture,” Journal of Semiconductor Technology and Science, vol. 10, no. 3, pp. 193 ~ 202, Sept. 2010. [PDF]
Sangho Yoon, Hanho Lee, Kihoon Lee, "High-Speed Two-Parallel Concatenated BCH-based Super-FEC Architecture for Optical Communications," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems, vol. E92-A, No. 4, pp.769-777, April, 2010. [PDF]
T-S. Kim, Hanho Lee, J. Park, C-H. Lee, Y-M. Lee, C-S. Choi, S-G. Hwang, H. D. Kim, C. H. Min, "Ubiquitous Evolvable Hardware System for Heart Diseases Diagnosis Applications," International Journal of Electronics, vol. 95, no. 7, pp. 637-651, July 2008. (SCI) [PDF]
Seungbeom Lee, Chang-Seok Choi, and Hanho Lee, "Two-parallel Reed-Solomon based FEC architecture for optical communications," IEICE Electronics Express (ELEX), vol. 5, no. 10, pp. 374-380, May 1. 2008. (SCIE) [PDF]
Jeesung Lee and Hanho Lee, "A High-Speed 2-Parallel Radix-2^4 FFT/IFFT Processor for MB-OFDM UWB Systems," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E91-A, no. 4, pp. 1206-1211, April 2008. (SCIE) [PDF]
Seungbeom Lee and Hanho Lee, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences . vol. E91-A, no. 3, pp. 830-835, March 2008. (SCIE) [PDF]
Chang-Seok Choi and Hanho Lee, "A Self- Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform," IEICE Transactions on Information and Systems, vol. E90-D, no. 12, pp. 1932-1938, Dec. 1. 2007. (SCIE) [PDF]
Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack, "A Design and Performance of 4-Parallel MB-OFDM UWB Receiver," IEICE Transactions on Communications, vol.E90-B, no. 3, pp. 672-675, March 2007. (SCI) [PDF]
Hanho Lee, Chang-Seok Choi, "Implementation of a FIR Filter on a Partial Reconfigurable Platform," KES2006, LNAI4253, Part III, pp. 108-115, Oct. 2006. (SCIE) [PDF]
Yeong-Jae Oh, Hanho Lee, Chong-Ho Lee, "Dynamic Partial Reconfigurable FIR Filter Design," Reconfigurbale Computing: Architectures and Applications (ARC 2006), LNCS3985, Mar. 2006. (SCIE) [PDF]
Hanho Lee, "Power-Aware Scalable Booth Multiplier," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 11, pp.3230-3234, Nov. 2005. (SCIE) [PDF]
Hanho Lee, "Reconfigurable Power-Aware Scalable Booth Multiplier," KES2005, LNAI, Part I, pp. 176-183, Sept. 2005. (SCIE) [PDF]
I. J. Jeon, P. K. Rhee, Hanho Lee, " An Evolvable Hardware System under Uneven Environment," KES2005, LNAI, Part II, pp. 319-326, Sept. 2005.(SCIE) [PDF]
Hanho Lee, " A High-Speed, Low-Complexity Reed-Solomon Decoder for Optical Communications ," IEEE Transactions on Circuits and Systems-II, vol. 52, No. 8, pp. 461-465, Aug. 2005. (SCI) [PDF]
Hanho Lee and G. E. Sobelman, VLSI Design of Digit-Serial FPGA Architecture, Journal of Circuits, Systems, and Computers , Vol. 13, No. 1, pp. 17-52, Feb. 2004. (SCIE) [PDF]
Hanho Lee and Asad Azam Pipelined Recursive Modified Euclidean Algorithm Block for Low-Complexity, High-Speed Reed-Solomon Decoder , IEE Electronics Letters , Vol. 39, No. 19, pp. 1371-1372, Sept 17. 2003. (SCI) [PDF]
Hanho Lee, High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder , IEEE Transactions on VLSI Systems , Vol. 11, No. 2, pp. 288-294, April 2003. [PDF]
Hanho Lee and G. E. Sobelman, "Performance Evaluation and Optimal Design for FPGA-Based Digit-Serial DSP Functions, An International Journal Computers & Electrical Engineering , Vol. 29, No. 2, pp. 357-377, March 2003.
Hanho Lee and G. E. Sobelman, "FPGA-Based Digit-Serial CSD FIR Filter for Image Signal Format Conversion, Microelectronics Journal , Vol. 33, pp. 501-508, April 2002.
Hanho Lee, Modified Euclidean Algorithm Block for High-Speed Reed-Solomon Decoder , IEE Electronics Letters , pp. 903-904, Vol. 37, No. 14, July 2001. [PDF]
Hanho Lee and G. E. Sobelman, "A Comparative Study of Glitch-free TSPC D flip-flop Circuits at a Low Supply Voltage, Microelectronics Journal , Vol.29, No.12, pp. 1025-1031, Dec. 1998.
Hanho Lee and G. E. Sobelman, "New XOR/XNOR and Full Adder Circuits for Low-Voltage, Low-Power Applications, Microelectonics Journal , Vol. 29, No.8, pp. 509-517, Aug. 1998.