Quang Dang Truong, and Hanho Lee. "Configurable Butterfly Unit Architecture for CKKS-based Fully Homomorphic Encryption", 2025 International SoC Design Conference (ISOCC), October 15-18, 2025. [PDF]
Muhammad Ogin Hasanuddin, and Hanho Lee. "Twiddle-Factor Generation Using Reused Butterfly Array for Fully Homomorphic Encryption", 2025 International SoC Design Conference (ISOCC), October 15-18, 2025. [PDF]
Hien Nguyen, Quang Dang Truong, Hanho Lee, and Tuy Tan Nguyen. "Scalable and High-Performance Number-Theoretic Transform Design for Lattice-Based Cryptography", 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), October 12-15, 2025. [PDF]
Quang Dang Truong, Tuy Tan Nguyen, and Hanho Lee. "Highly-Efficient Unified Polynomial Arithmetic Module Architecture for Falcon PQC Scheme", 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), October 12-15, 2025. [PDF]
Muhammad Ogin Hasanuddin, and Hanho Lee. "RNS Base Conversion Using Optimized Multiword Multipliers for Approximate Modulus Switching", 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), October 12-15, 2025. [PDF]
Muhammad Daffa Rasyid, Ardianto Satriawan, and Hanho Lee. "Comparison of Barrett Modular Reduction with Various Multipliers in the Context of BFV/BGV Homomorphic Encryption", 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), October 12-15, 2025. [PDF]
Yunseong Jang, Seulbee Yang, and Hanho Lee. "Live Demonstration: ML-KEM PQC Hardware Accelerator for Secure Video Encryption", 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), October 12-15, 2025. [PDF]
Muhammad Ogin Hasanuddin, Rafael Aditya Cahyo W., Infall Syafalni, Nana Sutisna, Hanho Lee, and Trio Adiono. “Base Conversion RNS Using Hybrid Barret-Karatsuba-Based Modulus Prime Cores for Homomorphic Multiplication,” 2025 IEEE International Symposium on Circuits and Systems (ISCAS), May 25-28, 2025. [PDF]
Rella Mareta, Ardianto Satriawan, and Hanho Lee. “An Efficient NTT-Based Polynomial Multiplication Architecture for BFV Homomorphic Encryption,” 2025 IEEE International Symposium on Circuits and Systems (ISCAS), May 25-28, 2025. [PDF]
Ardianto Satriawan, Rella Mareta, and Hanho Lee. “Exploring Possibilities of BFV-based Homomorphic Encryption for Privacy-Preserving Image Processing,” 2025 IEEE International Symposium on Circuits and Systems (ISCAS), May 25-28, 2025. [PDF]
Linh Nguyen, Cheol-Hong Min, Hanho Lee, and Tuy Nguyen. “Secure and Reliable 6G Communications with BCH-Based GLDPC and Kyber,” 43rd IEEE International Conference on Consumer Electronics (ICCE 2025), Las Vegas, USA, January 11-14, 2025. [PDF]
Quang Dang Truong and Hanho Lee, "Efficient Polynomial Arithmetic and Hash Modules" 2024 Asia Pacific Conference on Circuits And System (APCCAS), Taipei, Taiwan, Nov. 7-9. 2024. [PDF]
Hanyoung Lee, Hanho Lee, "Automorphism Architecture for Bootstrapping Homomorphic Encryption" 2024 International SoC Design Conference (ISOCC), Sapporo, Hokkaido, Japan, Aug, 2024. [PDF]
Rella Mareta, and Hanho Lee. "Compact 2 17 NTT Architecture for Fully Homomorphic Encryption." 2024 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, May 19-22, 2024. [PDF]
Chulwoo Lee, Hanyoung Lee, Phap Duong-Ngoc, and Hanho Lee, "Twiddle Factor Generator Architecture for Number Theoretic Transform" 2023 International SoC Design Conference (ISOCC), pp. 209-210, Jeju, Korea, Oct, 2023. [PDF]
Tuy Tan Nguyen, Jisu Kim, and Hanho Lee, "CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier," 56th IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, USA, May 21-25, 2023. [PDF]
Tuy Tan Nguyen and Hanho Lee, "Toward A Real-Time Elliptic Curve Cryptography Based Facial Security System" 2022 Asia Pacific Conference on Circuits And System (APCCAS), Shenzhen, China, Nov, 2022 [PDF]
Thang Xuan Pham, Phap Duong-Ngoc, Tuy Tan Nguyen and Hanho Lee, "Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders" 2022 International SoC Design Conference (ISOCC), pp. 105-106, Gangwon-do, Korea, Oct, 2022 [PDF]
Phap Duong-Ngoc, Thang Xuan Pham, Tuy Tan Nguyen and Hanho Lee, "Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption" 2022 International SoC Design Conference (ISOCC), pp. 259-260, Gangwon-do, Korea, Oct, 2022 [PDF]
Tuy Tan Nguyen, Thang Xuan Pham, Phap Duong-Ngoc, and Hanho Lee, "A Novel Performance Verification Approach of MIPI Camera Serial Interface 2" The 8th International Conference on Next Generation Computing 2022 (ICNGC), pp. 88-89, Jeju, Korea, Oct, 2022 [PDF]
Thang Xuan Pham, Tuy Tan Nguyen, Phap Duong-Ngoc, Huyen Pham Thi, Hanho Lee, "High-Throughput Multi-Threaded Non-binary LDPC Decoder Architecture"The 7th International Conference on Next Generation Computing 2021 (ICNGC), pp. 374-376, Jeju, Korea, Nov, 2021 [PDF]
Tuy Tan Nguyen, Phap Duong-Ngoc, Thang Xuan Pham, and Hanho Lee, "Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design" 2021 International SoC Design Conference (ISOCC), pp. 403-404, Jeju, Korea, Oct, 2021 [PDF]
Phap Duong-Ngoc, Tuy Tan Nguyen, and Hanho Lee, "Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption" 2021 International SoC Design Conference (ISOCC), pp. 345-346, Jeju, Korea, Oct, 2021 [PDF]
Thang Xuan Pham, and Hanho Lee, "High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule" 2021 IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea, May. 2021. [PDF]
Thang Xuan Pham, and Hanho Lee, "Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes" 2020 International SoC Design Conference (ISoCC2020), Yeosu, Korea, Oct. 2020. [PDF]
Phap Duong-Ngoc, Yong-Jin Kim, and Hanho Lee, "Efficient k-Parallel Pipelined NTT Architecture for Post Quantum Cryptography" 2020 International SoC Design Conference (ISoCC2020), Yeosu, Korea, Oct. 2020. [PDF]
Huyen Pham Thi, Cuong Dinh The, Nghia Pham Xuan, Hung Dao Tuan, Hanho Lee, "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder," IEEE Asia Pacific Conference on Circuits and Systems, pp.213-216, Bangkok, Nov. 11-14, 2019. [PDF]
Tuy Tan Nguyen, Yujin Hyun, Jisu Kim, Dongwoo Choi, and Hanho Lee, "Ring-LWE Based Face Encryption and Decryption System on a GPU," 2019 International SoC Design Conference (ISoCC2019), pp. 15-16, Jeju, Korea, Oct. 2019. [PDF]
Tram Thi Bao Nguyen and Hanho Lee, "Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture," 2018 International SoC Design Conference (ISoCC2018), pp. 210-211, Daegu, Korea, Nov. 2018. [PDF]
Huyen Pham Thi, H. D. Tuan, L. D. T. Dang, Hanho Lee, T. N. Huu, "Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding," 2018 International Conference on Advanced Technologies for Communications (ATC), pp. 292-295, Oct. 18. 2018. [PDF]
Tuy Tan Nguyen and Hanho Lee, "High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting," 2018 IEEE International Symposium on Circuits and Systems (ISCAS2018), Florence, Italy, May 28. 2018. [PDF]
Huyen Pham Thi and Hanho Lee, "Reduced-Complexity Trellis Min-Max Decoder for Non-Binary LDPC Codes," 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP2018), pp. 1179-1182, Calgary, Canada, April 16. 2018.[PDF]
Seunghun Oh and Hanho Lee, "Parallel Architecture for Concatenated Polar-CRC Codes," 2017 International SoC design conference (ISOCC), pp. 173-174, Nov. 5-8, 2017. [PDF]
Tuy Tan Nguyen and Hanho Lee, "A Delay-Efficient Ring-LWE Cryptography Architecture for Biometric Security," 2017 IEEE International Symposium on Circuits and Systems (ISCAS2017), pp. 2210-2213, Baltimore, MD, USA, May 2017. [PDF]
Huyen Thi Pham and Hanho Lee, "Low Latency Check Node Unit Architecture for Nonbinary LDPC Decoding," 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2016), pp. 400-401, Jeju, Nov. 2016.[PDF]
Taesung Kim, Seunghun Oh and Hanho Lee, "Low-Complexity Soft-Decision BCH Decoder Architecture," International Conference on Electronics, Information, and Communication (ICEIC) 2016, pp. 743-744, Danang, Vietnam, Jan. 2016.
Huyen Thi Pham, Sabooh Ajaz and Hanho Lee, "Parallel block-layered nonbinary QC-LDPC decoding on GPU," 2015 IEEE Workshop on Signal Processing Systems (SiPS), pp. 1-6, Hangzhou, China, Oct. 2015.[PDF]
Sabooz Ajaz and Hanho Lee, "Area Efficient Half Row Pipelined Layered LDPC Decoder for Gigabit Wireless Communications," International SoC Design Conference(ISoCC2015), pp. 287-288, Gyeongju, Korea, Nov. 2015.[PDF]
Tuy Tan Nguyen and Hanho Lee, "High-Speed Low-Complexity Elliptic Curve Cryptographic Processor," International SoC Design Conference (ISoCC2015), pp. 265-266, Gyeongju, Korea, Nov. 2015.[PDF]
Tram Thi Bao Nguyen and Hanho Lee, "Shared CSD Complex Constant Multiplier for Parallel FFT Processors," International SoC Design Conference (ISoCC2015), pp. 27-28, Gyeongju, Korea, Nov. 2015.[PDF]
Huyen Pham Thi, Sabooz Ajaz and Hanho Lee, "Efficient Min-MAx Nonbinary LDPC Decoding on GPU," International SoC Design Conference, pp. 266-267, Jeju, Korea, Nov. 2014.[PDF]
Sabooh Ajaz and Hanho Lee, "Multi-Gb/s Multi-Mode LDPC Decoder Architecture for IEEE 802.11ad Standard," 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014), pp. 153-156, Ishigaki Island, Okinawa, Nov. 17. 2014.[PDF]
Sabooh Ajaz and Hanho Lee, "Radix-3 Quasi Shift Network for Reconfigurable QC-LDPC Decoders," 2013 International SoC Design Conference (ISoCC2013), Busan, Nov. 17. 2013.[PDF]
Jewong Yeon, Hanho Lee, "High-Performance Iterative BCH Decoder Architecture for 100Gb/s Optical Communications," 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), pp. 1344-1347, Beijing, May 2013. [PDF]
Shin-il Lim, In-Sub Choi, Hanho Lee, “Biochemical Sensor Interface Circuits with Differential Difference Amplifier,” 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2012), pp. 176-179, Dec. 2-5, 2012.[PDF]
Jeong-In Park, Jewong Yeon, Seung-Jun Yang, and Hanho Lee, “An Ultra High-Speed Time-Multiplexing Reed-Solomon-based FEC Architecture,” International SoC Design Conference (ISOCC2012), pp. 451-454, Nov. 5. 2012. [PDF]
Seong-In Hwang, Hanho Lee, Shin-Il Lim, “A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS2012), pp. 1771-1774, Seoul, May 2012.[PDF]
Chang-Seok Choi, Hanho Lee, Noriaki Kaneda, Young-Kai Chen, “Concatenated Non-Binary LDPC and HD-FEC codes for 100Gb/s optical transport systems,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS2012), pp. 1783-1786, Seoul, May 2012. [PDF]
Yong-Kyu Kim, Cang-Seok Choi, Hanho Lee, and Jin-Gyun Chung, “Low-Complexity Filter and Interpolator Design for ATSC DTV Systems,” International SoC Design Conference (ISOCC2011), pp. 432 - 435, Nov. 17. 2011.[PDF]
Hyo-Jin Ahn, Chang-Seok Choi, Hanho Lee, “High-throughput variable-length Reed-Solomon decoder for high-rate WPAN applications,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, Seoul, Aug. 7. 2011. [PDF]
Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim and Gerald E. Sobelman, “A High-Throughput LDPC Decoder Architecture for High-Rate WPAN Systems,” 2011 IEEE International Symposium on Circuits and Systems (ISCAS2011), pp. 1311-1314, Rio de janeiro, May 2011. [PDF]
Taesang Cho, Hanho Lee, Jounsup Park and Chulgyun Park, "A High-Speed Low-Complexity Modified Radix-2^5 FFT Processor for Gigabit WPAN Applications,” 2011 IEEE International Symposium on Circuits and Systems (ISCAS2011), pp. 1259-1262, Rio de Janeiro, May 2011. [PDF]
Jeong-In Park, Hanho Lee and Seongsoo Lee,, "An Area-Efficient Truncated Inversionless Berlekamp-Massey Architecture for Reed-Solomon Decoders,” 2011 IEEE International Symposium on Circuits and Systems (ISCAS2011), pp. 2693-2696, Rio de Janeiro, May 2011. [PDF]
Ki-Sun Jung, Hanho Lee, “Low-cost variable-length FFT processor for DVB-T/H applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2010), pp. 752-755, Kuala Lumpur, Dec. 6-8, 2010. [PDF]
Kihoon Lee and Hanho Lee, “A High-Performance Concatenated BCH Code and Its Hardware Architecture for 100 Gb/s Long-haul Optical Communications,” International SoC Design Conference (ISOCC2010), pp. 428 ~ 431, Nov. 2010.[PDF]
Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee, “100Gb/s two-iteration concatenated BCH decoder architecture for optical communications,” IEEE Workshop on Signal Processing Systems (SiPS2010), pp.404-409, San Francisco, Oct. 6-8, 2010.[PDF]
Chang-Seok Choi, Hanho Lee, "High Throughput Four-Parallel RS Decoder Architecture for 60GHz mmWave WPAN Systems," 28th International Conference on Consumer Electronics 2010, pp.225-256, Las Vegas, Jan. 11-13, 2010.[PDF]
Jeong-In Park, Chang-Seok Choi, Hanho Lee, “16-channel three-parallel Reed-Solomon based FEC architecture for 100Gb/s optical communications,” 2010 Internatonal Conference on Electronics, Information, and Communication (ICEIC), pp.414-416, June 2010.[PDF]
Hyo-Jin Ahn, Chang-Seok Choi, Hanho Lee, "High-Speed Low-Complexity Folded Degree-Computationless Modified Euclidean Algorithm Architecture for RS Decoders," 12th International Symposium on Integrated Circuits (ISIC2009), pp.582-585, Singapore, Dec. 14-16, 2009.[PDF]
Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, "Low-Complexity Folded FIR Filter Architecture for ATSC DTV Tuner," International SoC Design Conference, pp.569-572, Busan, Nov. 23-24, 2009.[PDF]
Jeong-In Park, Kihoon Lee, Chang-Seok Choi, Hanho Lee, "High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm," International SoC Design Conference, pp.452-455, Busan, Nov. 23-24, 2009. (IEEK Best Paper Award)[PDF]
Jin-Kyu Chang, Hanho Lee, Chang-Seok Choi, "A Power-Aware Variable-Precision Multiply-Accumulate Unit," 9th International Symposium on Communication and Information Technology 2009 (ISCIT'2009), pp. 1336-1339, Incheon, Sept. 28-30, 2009. [PDF]
Sangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je-Soo Ko, "Two-parallel Concatenated BCH Super FEC Architecture for 100-Gb/s Optical Communications," IEEE Workshop on Signal Processing Systems (SiPS2009), pp. 36-39, Tampere, Finland, Oct. 7~9, 2009. [PDF]
Chang-Seok Choi and Hanho Lee, "High-Speed Low-Complexity Three-Parallel Reed-Solomon Decoder for 6-Gbps mmWave WPAN Systems," European Conference on Circuits Theory and Design 2009 (ECCTD'09), pp. 515-518, Antalya, Turkey, August 23~27, 2009. [PDF]
Liu Hang and Hanho Lee, "A High Performance Four-Parallel 128/64-point Radix-2^4 FFT/IFFT Processor for MIMO-OFDM Systems," 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2008), pp. 834-837, Macau, Nov. 30. 2008. [PDF]
Seungbeom Lee, Change-Seok Choi, Hanho Lee, Jongyoon Shin, Je-Soo Ko, "40-Gb/s Two-Parallel Reed-Solomon based Forward Error Correction Architecture for Optical Communications,"2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2008), pp. 882-885, Macau, Nov. 30. 2008. [PDF]
Sangmin Kim, Gerald E. Sobelman, and Hanho Lee, "Flexible LDPC Decoder Architecture for High-Throughput Applications," 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2008), pp. 45-48, Macau, Nov. 30. 2008. [PDF]
Hanho Lee, Chang-Seok Choi, J. Shin, J-S. Ko, "100-Gb/s Three-Parallel Reed-Solomon based Forward Error Correction Architecture for Optical Communications," International SoC Design Conference, pp. 265-268, Busan, Nov. 24-25, 2008. [PDF]
Sangho Yoon and Hanho Lee, "A Discrepancy Computationless RiBM Algorithm and Its Architecture for BCH Decoders," 21st Annual IEEE International SoC Conference , pp. 379-382, Newport Beach, Sept. 17-20. 2008. [PDF]
Liu Hang and Hanho Lee, "High-Speed Four-Parallel 64-Point Radix-2^4 MDF FFT/IFFT Processor for MIMO-OFDM Systems," The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008), pp. 1469-1472, July 6-9. 2008. [PDF]
Minhyeok Shin, Hanho Lee, "A High-Speed Four-Parallel Radix-2^4 FFT/IFFT Processor for UWB Applications," 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 960-963, Seattle, May 18-21. 2008. [PDF]
Yong-Je Goo, Hanho Lee, "A 2 Bit-Level Pipelined Viterbi Decoder for High-Performance UWB Applications," 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 1012-1015, Seattle, May 18-21. 2008. [PDF]
Sangmin Kim, Gerald E. Sobelman, and Hanho Lee, "Adaptive Quantization in Min-Sum based Irregular LDPC Decoder," 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 536-539, Seattle, May 18-21. 2008. [PDF]
Hanho Lee and Minhyeok Shin, " A High-Speed Low-Complexity Two-Parallel Radix-2^4 FFT/IFFT Processor for UWB Applications," IEEE Asian Solid-State Circuits Conference, pp. 284-287, Jeju Korea, Nov. 12. 2007. [PDF]
Chang-Seok Choi and Hanho Lee, "A Partial Self- Reconfigurable Adaptive FIR Filter System," IEEE Workshop on Signal Processing Systems (SiPS'07), pp. 204-209, Sanghai, Oct. 17-19. 2007. [PDF]
Yong-Je Goo, Hanho Lee, "Modified 2bit-level Pipelined 2-Look-ahead Add-Compare Select Unit for High-Speed Viterbi Decoders," The 22nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2007), pp.1245-1246, July 2007. [PDF]
Liu Hang, Hanho Lee, "A Performance Analysis of 2-Parallel MB-OFDM UWB Receiver," The 22nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2007), pp. 523-524, July 2007. [PDF]
Minhyeok Shin, Hanho Lee, "A Power-Aware Scalable Pipelined Multiply-Accumulate Unit with Dadda Reduction Network," The 22nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2007), pp. 199-200, July 2007. [PDF]
Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 901-904, New Orleans, May 27-30. 2007. [PDF]
Y-M. Kim, C-S. Choi, S-G. Hwang, H. Y. Kim, C. H. Min, J-H. Park, Hanho Lee, T-S. Kim, C-H. Lee, "Ubiquitous Evolvable Hardware System for Heart Diseases Diagnosis Applications," ARC 2007, LNCS 4419, pp. 283-292, March 27-29, 2007. [PDF]
Jeesung Lee, and Hanho Lee, "A High-Speed 2-Parallel Radix-2^4 FFT/IFFT Processor for MB-OFDM UWB Applications," International SoC Design Conference (ISOCC), Chip Design Contest, Seoul, Oct. 26-27, 2006.
Hanho Lee, Jae-Hyun Park, Yong-Min Lee, Chang-Seok Choi, Jin-Tack Choi, Seung-Kon Hwang, Chong-Ho Lee, Duk-Jin Chung, Tae-Seon Kim, Hyun-Dong Kim, "Reconfigurable Evolvable Hardware for Adaptable Heart Diseases Diagnosis System," International SoC Design Conference (ISOCC), Seoul, pp. 537-540, Oct. 2006. (Best-paper award)
Chang-Seok Choi, and Hanho Lee, "An Reconfigurable FIR FIlter Design on a Partial Reconfigurable Platform," First International Conference on Communications and Electronics (HUT-ICCE 2006), Hanoi-Vietnam, Oct. 10-11, 2006.
Seong-Woo Choi, Sang-Sung Choi, Hanho Lee, "A FEC Architecture for UWB Systems," IEEE Vehicular Technology Conference (VTC) 2006 Fall, Sept. 2006. [PDF]
Sung-Woo Choi, Sang-Sung Choi,'Hanho Lee, "RS decoder architecture for UWB," International Conference on Advanced Communication Technology 2006 (ICACT 2006), vol. 1, pp. 805-808, Feb. 2006. [PDF]
Young-Jae Oh, Hanho Lee, Chong-Ho Lee, "A Reconfigurable FIR filter design for Dynamic Partial Reconfiguration," IEEE International Symposium on Circuits and Systems, Kos Greece, pp. 4851-4854, Kos-Greece, May 2006. [PDF]
Jeesung Lee, Hanho Lee, Sang-In Cho, Sang-Sung Choi, "A High-Speed, Low-Complexity Radix-2^4 FFT Processor for MB-OFDM UWB Systems," IEEE International Symposium on Circuits and Systems, Kos-Greece, pp. 4719- 4722, May 2006. [PDF]
Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack, "A High-Speed Receiver Architecture for MB-OFDM UWB Communications," International SoC Design Conference (ISOCC), Seoul, pp. 441-444, Oct. 2005. [PDF]
Yeong-Jae Oh, Chang-Seok Choi, Hanho Lee, Chong-Ho Lee, "A Reconfigurable CSD FIR Filter Design using Dynamic Partial Reconfiguration," International SoC Design Conference (ISOCC), Seoul, pp. 381-384, Oct. 2005. [PDF]
Hanho Lee, "An Ultra High-Speed Reed-Solomon Decoder," IEEE International Symposium on Circuits and Systems, Kobe Japan, pp. 1036-1039, May. 2005. [PDF]
Hanho Lee' , "A Power-Aware Scalable Pipelined Booth Multiplier", Proc. of IEEE International System-on-Chip (SOC) Conference , Santa Clara-USA, Sept. 12, 2004. [PDF]
Hanho Lee , and Asad Azam, " A Low-Complexity, High-Speed Reed-Solomon Decoder ", Proc. of IEEE International System-on-Chip (SOC) Conference , pp. 127-130, Portland, Sept. 17, 2003. [PDF]
Hanho Lee , High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder , Proc.of IEEE International Symposium on Circuits and Systems , Vol. 2, pp. 320-323, Bangkok, May 25. 2003. [PDF]
Hanho Lee , An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder , Proc. of IEEE Computer Society Annual Symposium on VLSI , pp. 209-210, Tampa, Feb. 2003. [PDF]
Hanho Lee , A VLSI Design of a High-Speed Reed-Solomon Decoder, Proc. of IEEE International ASIC/SOC conference , Washington DC., pp. 316-320, Sept. 2001. [PDF]
Hanho Lee , M. L. Yu and L. L. Song, VLSI Design of Reed-Solomon Decoder Architectures, Proc. of IEEE International Symposium on Circuit and Systems , Vol. 5, pp. 705-708, May. 2000. [PDF]
L. Gao, S. Shrivastava, Hanho Lee , and G. E. Sobelman, A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor, Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99) , pp. 304-305, April. 1999. [PDF]
Hanho Lee , J. Chung and G. E. Sobelman, "FPGA-Based Digit-Serial CSD FIR Filter for Image Signal Format Conversion," International Conference on Signal Processing Applications and Technology (ICSPAT'98) , pp. 689-693, Sept. 1998.
Hanho Lee and G. E. Sobelman, ``Digit-Serial Reconfigurable FPGA Logic Block Architecture, 1998 IEEE Workshop on Signal Processing Systems (SiPS'98) , pp. 469-478, Oct. 8-10, 1998.
Hanho Lee and G. E. Sobelman, ``Digit-Serial DSP Library for Optimized FPGA Configuration, Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'98) , pp. 322-323, April 15. 1998.
Hanho Lee , S. Shrivastava and G. E. Sobelman, ``FPGA Logic Block Architecture for Digit-Serial DSP Applications, Proc. of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'98) , pp. 257, Feb. 22-24, 1998.
Hanho Lee and G. E. Sobelman, ``FPGA-based FIR Filters Using Digit-Serial Arithmetic, Proc. of IEEE 1997 International ASIC Conference , pp.225-228, Sept. 1997.
Hanho Lee and G. E. Sobelman,``New Low-Voltage Circuits for XOR and XNOR, Proc. of IEEE Southeast Conference'97, pp. 225-229, April 1997.
Hanho Lee and G. E. Sobelman, "A New Low-Voltage Full Adder Circuit, Proc. of 7th Great Lakes Symposium on VLSI'97 , pp. 88-92, March 1997.