Prof. Hiroshi Iwai
NCTU, Hsinchu, Taiwan
Tokyo Institute of Technology, Yokohama, Japan
End of CMOS miniaturization and world after that
Recent smart society has been conducted by the progress of semiconductor technologies, especially by that of CMOS miniaturization. However, it is afraid that the CMOS miniaturization will reach its limit substantially in several years. In this talk, the limit of the CMOS miniaturization is explained and the world after reaching the limit is discussed.
Prof. Hiroshi Iwai is a vice-dean and distinguished chair professor at NCTU, Hsinchu, Taiwan. He is a semiconductor device engineer who received BE and Ph.D degrees from Univ. of Tokyo. He worked at Toshiba for 26 years from 1973 and at Tokyo Institute of Technology for 20 years since 1999, engaged in the development of high-density memories and logic/RF/photovoltaic/power devices.
Especially, he has contributed to the miniaturization of MOSLSI devices. He is a life fellow of IEEE and served as an IEEE EDS president and a Division I Director.
Prof. Juin J. Liou
Chair Professor, School of Information Engineering, Zhengzhou University, China
Chang Jiang Scholar Endowed Professor, Ministry of Education, China
Fellow of IEEE, Fellow of IET
Electrostatic Discharge (ESD) Protection for RF/High-Speed Integrated Circuits: Challenges and Solutions
Electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and hence more than 35% of single-event catastrophic chip damages can be attributed to the ESD event. This is a problem with increasing significance in modern and future nanoscale technologies in the context of diminishing device dimensions. As such, designing on-chip ESD structures to protect integrated circuits against the ESD stress is a high priority in the semiconductor industry. The continuing scaling of CMOS technology makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical and essential factor to the successful advancement and commercialization of the next-generation CMOS-based electronics.
The development of RF electronics went almost unnoticed until early 1980’s because, unlike Si VLSI, there were no mass consumer markets for such applications. Recently, this has been changed drastically due to the explosive growth in the civil wireless communications and internets. The modern RF integrated circuits are typically operated in a voltage range of 2-4 V. This relatively low-voltage operation, together with the low tolerance of parasitic capacitance at the I/O pins and the continuing scaling in CMOS process, imposes certain challenges to the design and optimization of RF ESD protection solutions.
An overview on the ESD sources, models, protection schemes, and testing will first be given in this talk. This is followed by presenting recent advancements and challenges on developing robust ESD protection solutions for modern low-voltage RF integrated circuits, as well as explorations and evaluations of ESD protection solutions in sub-28nm CMOS technologies.
Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering at the University of Central Florida (UCF), Orlando, Florida where he held the positions of Pegasus Distinguished Professor, Lockheed Martin St. Laurent Professor, and UCF-Analog Devices Fellow. His research interests are electrostatic discharge (ESD) protection design, modeling and simulation, and characterization. Currently, he works as the president of Emoat, LLC, a consulting firm which provides know-how and expertise on the design and characterization of ESD solutions. He also serves as a chair professor of Zhengzhou University, China and endowed professor of Zhejiang University, China.
Dr. Liou holds 55 patents and has published 13 books (1 more in press), more than 290 journal papers (including 21 invited review articles), and more than 240 papers (including more than 110 keynote and invited papers) in international and national conference proceedings. He has been awarded more than $14.0 million of research contracts and grants from federal agencies (i.e., NSF, DARPA, Navy, Air Force, NASA, NIST), state government, and industry (i.e., Semiconductor Research Corp., Intel Corp., Intersil Corp., Lucent Technologies, Alcatel Space, Conexant Systems, Texas Instruments, Fairchild Semiconductor, National Semiconductor, Analog Devices, Maxim Integrated Systems, Allegro Microsystems, RF Micro Device, Lockheed Martin), and has held consulting positions with research laboratories and companies in the United States, China, Japan, Taiwan, and Singapore. In addition, Dr. Liou has served as a technical reviewer for various journals and publishers, general chair or technical program chair for a large number of international conferences, regional editor (in USA, Canada and South America) of the Microelectronics Reliability journal, and guest editor of 7 special issues in the IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Microelectronics Reliability, Solid-State Electronics, World Scientific Journal, and International Journal of Antennas and Propagation.
Dr. Liou received ten different awards on excellence in teaching and research from the University of Central Florida (UCF) and six different awards from the IEEE. Among them, he was awarded the UCF Pegasus Distinguished Professor (2009) – the highest honor bestowed to a faculty member at UCF, UCF Distinguished Researcher Award (four times: 1992, 1998, 2002, 2009), UCF Research Incentive Award (three times: 2000, 2005, 2010), IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award in 2004 for exemplary engineering teaching, research, and international collaboration, and IEEE Electron Devices Society Education Award in 2014 for promoting and inspiring global education and learning in the field of electron devices. His other honors are Fellow of IEEE, Fellow of IET, Fellow of Singapore Institute of Manufacturing Technology, Fellow of UCF-Analog Devices, Distinguished Lecturer of IEEE Electron Device Society (EDS), and Distinguished Lecturer of National Science Council. He holds several honorary professorships, including the Chang Jiang Scholar Endowed Professor of Ministry of Education, China – the highest honorary professorship in China, NSVL Distinguished Professor of National Semiconductor Corp., USA, International Honorary Chair Professor of National Taipei University of Technology, Taiwan, Honorary Endowed Professor of National Taiwan University of Science and Technology, Taiwan, Chang Gung Endowed Professor of Chang Gung University, Taiwan, Feng Chia Chair Professor of Feng Chia University, Taiwan, Chunhui Eminent Scholar of Peking University, China, Cao Guang-Biao Endowed Professor of Zhejiang University, China, Honorary Professor of Xidian University, China, Consultant Professor of Huazhong University of Science and Technology, China, and Courtesy Professor of Shanghai Jiao Tong University, China. Dr. Liou was a recipient of U.S. Air Force Fellowship Award and National University Singapore Fellowship Award.
Dr. Liou has served as the IEEE EDS Vice-President of Regions/Chapters, IEEE EDS Treasurer, IEEE EDS Finance Committee Chair, Member of IEEE EDS Board of Governors, and Member of IEEE EDS Educational Activities Committee.
Prof. Cary Y. Yang
Electrical Engineering, Santa Clara University
Center for Nanostructures, Santa Clara University
Director of TENT Laboratory, Santa Clara University
Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, cobalt, ruthenium, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) has been demonstrated to be a serious contender in on-chip interconnect via. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure is conceived and fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNT-graphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood.
Our test structure consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low- pressure PECVD chamber, before being transferred onto an oxide-covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a recipe similar to that in our previous work on CNT vias with chromium underlayer, resulting in a 3D all-carbon interconnect structure. Scanning and transmission electron microscopy images reveal CNT alignment and interfacial nanostructure comparable to the CNT-Cr interface in CNT via. The measured resistance of the 3D structure is compared with those of sub-100 nm linewidth CNT vias. Our results demonstrate the feasibility of fabricating a 3D CNT/graphene device, which can serve as the building block for all- carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes.
Cary Y. Yang received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Pennsylvania. After working at M.I.T., NASA Ames Research Center, and Stanford University on electronic properties of nanostructure surfaces and interfaces, he founded Surface Analytic Research, a Silicon Valley company focusing on sponsored research projects covering various applications of surfaces and nanostructures. He joined Santa Clara University in 1983 and is currently Professor of
Electrical Engineering and Director of TENT Laboratory, a SCU facility located inside NASA Ames. He was the Founding Director of Microelectronics Laboratory and Center for Nanostructures, and served as Chair of Electrical Engineering and Associate Dean of Engineering at Santa Clara. His research spans from silicon-based nanoelectronics to nanostructure interfaces in electronic, biological, and energy-storage systems. An IEEE Life Fellow, he served as Editor of the IEEE Transactions on Electron Devices, President of the IEEE Electron Devices Society, and elected member of the IEEE Board of Directors. He was appointed Vice Chair of the IEEE Awards Board in 2013 and 2014. He received the 2004 IEEE Educational Activities Board Meritorious Achievement Award in Continuing Education "for extensive and innovative contributions to the continuing education of working professionals in the field of micro/nanoelectronics," and the 2005 IEEE Electron Devices Society Distinguished Service Award. From 2008 to 2013, he held the Bao Yugang Chair Professorship at Zhejiang University in China.