Prof. Jenn-Gwo Hwu
Department of Electrical Engineering / Graduate Institute of Electronics Engineering,
National Taiwan University, Taiwan.
Negative Transconductance in Coupled MIS(p) Tunnel Diodes with Concentric Gate Structure
In this work, the authors want to present the coupling effect between two neighboring devices. An MIS structure with ultra-thin oxide was used as an effective sensor to sensing the supply of minority carriers coming from the neighboring device. A concentric ring structure of MIS device surrounding the sensor was adopted and gives various extents of minority carriers to the central sensor. It was found that under certain range of oxide thickness, the amounts of injection minority carriers and inversion carriers are in competition which makes the sensor current exhibits negative transconductance behavior. The fundamental physics of MIS sensing mechanism and the coupling effect were described in this talk. Possible applications of negative transconductance with tunable designed biasing were also presented.
Dr. Jenn-Gwo Hwu was born in Tainan, on August 29, 1955. He received the B.S. degree in electronic engineering from National Chiao-Tung University in 1977 and the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University in 1979 and 1985, respectively. In 1981, he joined the faculty of National Taiwan University, where he is currently a Professor with the Department of Electrical Engineering and with the Graduate Institute of Electronics Engineering. On August 2006, he was appointed as the Distinguished Professor of NTU. He was the Chairperson of the Department of Electrical Engineering, NTU, since August 2007 till July 2010. His recent research interests are MIS tunnel diode with ultra-thin gate oxide, transient behavior in MIS current, volatile memory application using MIS structure, and coupling effect between two MIS devices. Dr. Hwu was honored with an Outstanding Teaching Award from NTU and Outstand Research Award from MOST. He was also awarded the Himax Chair Professorship at NTU.
Prof. Steve S. Chung
Chair Professor, National Chiao Tung University, Taiwan.
1T Resistance Switching Memory for 28nm and Beyond Embedded HKMG Generations
In the research of the replacement for Floating gate and SONOS, RRAM seems to be a potential candidate because of simple implementation and the easy integration with the VLSI process. However, the time-to-market for RRAM seems to be slowed down as a result of sneak path, forming current, and uniformity issues, especially at the circuit level.
In this talk, I will address a one transistor resistance-switching nonvolatile memory which is feasible for the 28nm CMOS compatible technology and beyond, which provides an excellent solution for the future NVM technology which do not need to have a concern of charge loss issue and the sneak path problem. These architectures are superior to the 1st generation floating-gate and the 2nd generation SONOS NVMs, and are fully compatible with the logic CMOS technology and well-suited for both NOR and NAND memories, especially for future embedded applications.
STEVE S. CHUNG received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering. His Ph.D. thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.
Currently, he is NCTU and UMC Chair Professor at the National Chiao Tung University (NCTU). After joining NCTU in 1987, he has been the first Department Head of EECS Honors Program (2004-2005), Dean of International Affairs Office and Executive Director of school level research center, (2007-2008). He was a Visiting Prof. to both Stanford University and University of California-Merced, and taught graduate courses at both universities. He has been the consultant to the two world largest IC foundries, TSMC and UMC. His recent current research areas include- FinFET, TFET, nonvolatile memory technology and reliability; and reliability physics/interface characterization. He was the first speaker (from Taiwan) to present the paper at VLSI Technology symposium in 1995 and has more than 27 times presentation at IEDM/VLSI.
He is an IEEE Fellow, IEEE Distinguished Lecturer, EDS Taipei chapter chair, and with past involvement as EDS BoG(Board of Governor) (2004-2017), EDS Regions/Chapters Vice-Chair and chair, and Editor of EDL(2002-2008). The current Editor of J-EDS, Editor of Applied Physics-A. He was the recipient of 3 times outstanding research award He has served on various important conference committees, e.g., VLSI Technology, IEDM, IRPS, IPFA, ICMTS, SNW, VLSI-TSA, SSDM etc. He was awarded 3 times outstanding Research Award, and distinguished NSC Research Fellow, from the National Science Council; Distinguished EE Professor and Engineering Professor of the Engineering Societies in Taiwan. He received 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.
Prof. Pei-Wen Li
Institute of Electronics Engineering, National Chiao Tung University, Taiwan.
Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables monolithically-integrated Ge-based receivers on Si platform
We report self-organized gate stacksof Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO2 thickness (2–4nm), and Ge content (x=0.65-0.85) and strain engineering (comp= 1-3%) of the Si1-xGex are achieved. Size-tunable photo-luminescence (PL) of 300-1600nm are observed on 5–100nm Ge NPs. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.
Pei-Wen Li received the Bachelor degree in Electrophysics from National Chiao-Tung University in 1989, and received the Master and Ph.D. degree in Electrical Engineering from Columbia University in New York in 1991 and 1994, respectively. Her Ph.D. dissertation was focused on the study of low temperature oxidation of SiGe alloys and she has successfully demonstrated the first pure SiGe-channel pMOSFETs “SiGe pMOSFETs with gate oxide fabricated by microwave electron cyclotron resonance plasma”, IEEE Electron Device Letters, vol. 15, p.402-405 (cited time: 46). In 1995, she joined the R/D technology division of Vanguard International Semiconductor Corporation working on the process development and integration of 64M DRAM. Then, she joined I-Shou University as a faculty in the department of Electronic Engineering in 1996, where her research was focused on the characterization of InGaAsN material properties and its application on HEMT and HBT related devices. She joined the department of Electrical Engineering, National Central University as an associate professor in 2000, was promoted to be a professor since August 2005, and served as the department chairman during 2007-2010. Currently she is the associated dean of Academic affairs and the director of the Center for Nanoscience and Technology, National Central University in charge of the core facility for nano fabrication and nano characterization.
Dr. Li’s main research theme focuses on experimental silicon-germanium nanostructures and devices. Her present research encompasses germanium quantum dot single electron transistors, photodetectors, nonvolatile memory, and energy saving (photovoltaic and thermoelectric) devices, making use of self-assembly nanostructures in silicon integration technology. Her research group has successfully developed a novel CMOS-compatible, self-organized approach for the generation of designer germanium quantum dots (desired size, location, and depth of penetration) within Si-containing layers using the control available through lithographic patterning and selective oxidation of nanopatterned silicon-germanium-on-insulator structures. Of particular, the successful demonstration of precise placement and size control of the self-assembled germanium quantum dots shed light on the practical creation of new nano-electronic, nano-photonic, and electromechanical devices..
She has produced the first Ge quantum-dot single electron transistor with self-aligned nanoelectrodes that produces room-temperature Coulomb blockade characteristics with very large peak-to-valley ratio up to 750 and excellent Coulomb stability (“Fabrication of a germanium quantum-dot single electron transistor with large Coulomb-blockade oscillations at room temperatures,” Applied Physics Letters, vol. 85, p. 1532 (2004), “Tunneling spectroscopy of germanium quantum-dot in single-hole transistors with self-aligned electrodes,” Nanotechnology, vol. 18, p. 475402 (2007), “Single Ge quantum dot placement along with self-aligned electrodes for effective management of single charge tunneling,” IEEE Trans. Electron Devices, vol. 59, p. 3224 (2012), and “Designer Ge quantum dot Coulomb blockade thermometry,“ Appl. Phys. Lett., vol. 104, 243506 (2014).
She has also successfully demonstrated size-tunable from near ultraviolet (NUV) to near infrared (NIR) Ge quantum-dot photodetectior in 20122015 (“CMOS-compatible generation of self-organized 3D Ge quantum dot array for photonic and thermoelectric applications,” IEEE Trans. Nanotechnology, vol. 11, no. 4, p. 657-660, “Size tunable Ge quantum dot metal-oxide-semiconductor photodiodes with low dark current and high responsivity for near ultraviolet to visible applications,” Nanoscale, 6 (10), 5303 – 5308, and, “Designer germanium quantum dot phototransistor for near infrared optical detection and amplification,” Nanotechnology, vol. 26, 055203 (2015)).
Prof. Wen-Kuan Yeh
Department of Electronic Engineering, Chiao-Tung University, Taiwan
Deputy Director-General, National Nano Device Laboratories
New Paradigm of Nano Device
As MOSFETs are scaled down to sub-5nm and below, power consumption is the major limitation to maintain device performance well. Thus, how to suppress the device’s sub-threshold leakage and gate leakage is the key issue for sub-5nm MOSFET especially for high performance/lower power system. In order to scale MOSFET following Moore’s law continuously, there are some candidates are introduced to replace conventional CMOS including FinFET, GAA transistor, 2D FET and NCFET. This talk will explain semiconductor nano device trend and related advanced technology development especially for coming 3nm technology regime. And other specific device for more than Moore application for sensor, energy harvesting and Internet on Thing (IoT) will be also explained.
Wen-Kuan Yeh was born in Hsinchu, Taiwan in 1964. He received his Ph.D. in electronics engineering from National Chiao-Tung University, Taiwan in 1996. In 1989-90, he worked at Taiwan Semiconductor Manufacturing Corporation (tsmc) Research and Development Division, as a research assistant to work on sub-um CMOSFET and his M.S. thesis. During 1996 to 2000, He joined Unite Microelectronic Corporation (UMC), Technology & Process Development Division as a Research Scientist. He is currently a full professor of Electrical Engineering Department at National University of Kaohsiung, and also serves as the General Director of National Nano Device laboratories (NDL) and Chip Implementation Center (CIC). He is a Chair of IEEE EDS Tainan Chapter. He has published 6 edited books, over 200 peer reviewed papers, 6 book chapters, and over 100 patents. His recent work is focused on the field of nano-scaled FinFETs, GAA FET, and 2D FET.
Prof. Siegfried Selberherr
Institute for Microelectronics, TU Wien, Austria.
A Single Spin-Switch
Spin correlations at hopping are known to be responsible for large magnetoresistance at trap-assisted tunneling between normal metal and ferromagnetic electrodes. The reason is the spin-selective escape rate, which results in a non-zero average spin at a trap. Since the spin on a trap is a vector quantity, it produces unusual correlations in multi-terminal devices. We analyze a three-terminal device with ferromagnetic electrodes and demonstrate that the spin correlations result in current-voltage dependences characteristic to a single-electron transistor.
Professor Siegfried Selberherr was born in Klosterneuburg, Austria, in 1955. He received the degree of Diplomingenieur in electrical engineering and the doctoral degree in technical sciences from the Technische Universität Wien in 1978 and 1981, respectively. Dr. Selberherr has been holding the venia docendi on computer-aided design since 1984. Since 1988 he has been the Chair Professor of the Institut für Mikroelektronik. From 1998 to 2005 he served as Dean of the Fakultät für Elektrotechnik und Informationstechnik. Prof. Selberherr published more than 400 papers in journals and books, where more than 100 appeared in Transactions of the IEEE. He and his research teams achieved more than 1100 articles in conference proceedings of which more than 180 have been with an invited talk. Prof. Selberherr authored two books and co-edited more than 45 volumes, and he supervised, so far, more than 100 dissertations. His current research interests are modeling and simulation of problems for microelectronics engineering. Prof. Selberherr is a Fellow of the IEEE, a Fellow of the Academia Europaea, a Fellow of the European Academy of Science and Arts, and a Distinguished Lecturer of the IEEE Electron Devices Society.
Prof. Hei Wong
Department of Electronic Engineering, City University of Hong Kong, China.
On the Issues of High-k Scaling into the Subnanometer EOT Range
It was proposed that the equivalent oxide thickness (EOT) of gate dielectric film for the CMOS technologies a decade ago should be around half nanometer. However, even for the latest CMOS technology, we are still not able to achieve this scaling goal. The introduction of high-k dielectrics did enable gate EOT scaling down to the atomic scale for a couple generations but it has already lost its momentum because of material and technology limitations. Regardless the significant degradation in the electrical characteristics and reliability for the sub-nanometer EOT high-k dielectric films, the interface layer between the high-k/silicon and high-k/metal gate, which are not scalable, have become the ultimate limit for the smallest achievable EOT. This talk highlights the issues and challenges for the deep sub-nanometer gate dielectric EOT scaling.
Hei Wong received his Ph.D. in electrical and electronic engineering from the University of Hong Kong. Dr. Wong joined the faculty of the Department of Electronic Engineering at City University of Hong Kong in 1989 and is now a professor of the Department. Dr. Wong was the chair for the IEEE ED/SSC Hong Kong Joint Chapter during 2002-2003. He is a member of the international steering committees, technical program committees, and organizing committees for many international and local conferences. Dr. Wong has served as editor or guest editor for many journals including Microelectronics Reliability (Elsevier), IEEE Transactions on Electron Devices, IEEE Transactions on Nanotechnology. He served as Regional Editor for IEEE EDS Newsletter during 2003-2009. He has served as a Distinguished Lecturer for IEEE EDS since 2002. Dr. Wong has worked on MOS device modeling and characterization, hot-electron effects, low-frequency noise, thin dielectric film physics, IC process modeling and characterization, MOS integrated circuit designs, solid-state sensors. He is author or co-author of four books and over 350 papers. He has presented many invited talks and keynote speeches at numerous international conferences.
Dr. Wong is author or co-author of four books and over 350 papers including over 170 journal papers, dozen journal review papers and has presented many invited talks and keynote speeches at numerous international conferences.
Prof. Chenhsin Lien
Department of Electrical Engineering of National Tsing Hua University
High Performance WSe2 Transistors with Multilayer Graphene Source/Drain
We demonstrate p-type FETs based on graphene-WSe2 lateral heterojunctions by CVD technique. Multilayer graphene (MLG) is adopted to reduce contact resistance while the channel is still a WSe2 monolayer. Furthermore, by imposing doping to graphene S/D, Ion/Ioff ratio to enhanced to 10^8 and the unipolar p-type characteristics are obtained regardless the work function of the metal in ambient air condition.
Dr. Chenhsin Lien is the Professor of the Department of Electrical Engineering of National Tsing Hua University (NTHU). He is the Director of the Center of the Advanced Power Technologies of NTHU. Throughout his career, his research has primarily focused on the solid-state devices ranging from the quantum optoelectronic devices, CMOS devices, nanoelectronic devices to memories. Dr. Lien received the BS degree in Physics in 1975 from National Tsing Hua University, Hsinchu, Taiwan and the PhD degrees in Physics in 1982 from the Ohio State University, U.S.A.. Since 1983 he has been with the Department of Electrical Engineering of NTHU, Hsinchu, Taiwan. From 2004 to 2006, he was the Director of the Institute of Electronic Engineering of NTHU. From 2006 to 2010, he was the Chair of Department of Electrical Engineering of NTHU. During 2010, he was the Acting Dean of the College of Electrical Engineering and Computer Science of NTHU, Dr. Lien has published more than 100 technical papers. His recent research interests including the studies of 2D semiconductor devices and nonvolatile memories.
Prof. Chao-Sung Lai (賴朝松)
Senior Member, IEEE
Department of Electronic Engineering, Chang Gung University, Taiwan
Department of Nephrology, Chang Gung Memorial Hospital, Taiwan
Graphene Based Materials for Memory, Sensor and Memristor
A novel graphene based insulator, fluorographene, is firstly applied as gate dielectric in a field effect transistor. To identify the dielectric quality, dielectric constant, breakdown electric field and thermal stability are investigated. In this talk, the scalable and one-step fabrication of single atomic-layer transistors is demonstrated by the selective fluorination of graphene using a low-damage CF4 plasma treatment, where the generated F-radicals preferentially fluorinated the graphene at low temperature (<200°C) while defect formation was suppressed by screening out the effect of ion damage. The fluorographene was also used as decoupling for graphene as its substrate and mobility was improved much. Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 10¹¹ cm⁻² and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates NH⁺ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates. Moreover, the pH, pNa ion sensing properties of graphene based ion-sensor by nickel end contact modification were demonstrated. The pH and pNa sensitivities were around 36.5mV/pH and 15.3mV/pNa, respectively, for pristine graphene. For Ni end-contact modified graphene, sensitivities are changed to 41mV/pH and no pNa sensitivity. A graphene-based memristor with high out-of-plane resistance and a large resistance ratio between high and low resistance states was demonstrated by taking advantage of the weak surface van der Waals interaction of graphene will be introduced in this talk.
Chao-Sung Lai received the B.S. and Ph.D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1996, respectively. In 1996, he joined National Nano Device Laboratories, Hsinchu, where was engaged in the research of silicon-on-insulator devices. He then, in 1997, joined Chang Gung University as a faculty in the department of electronic engineering. He has been engaged in the research of the characterization and reliability of MOSFETs, Flash memory and transistor based biosensors. From 2001 to 2002, he visited the Department of Electrical Engineering, University of California, Berkeley, for visiting research on fin-shaped FETs. Since 2007 to 2013, he had been the Chairman of the Department of Electronic Engineering and the Director of the Biosensor Group of the Biomedical Research Center, Chang Gung University, for the research-related bio-transistor application on ions, proteins, DNA, and biomarker analysis. From 2012 till now, he is the Dean of Engineering College of Chang Gung University. He holds 11 U.S. patents and 60 Taiwan patents, and he is the author of more than 350 SCI journal and conference papers, 25 international invited talks, and 2 book chapters. He is the Leading Guest Editor of the SCI journals, including Microelectronics Reliability (2010), Nano-Scaled Research Letters (2011), and Solid-State Electronics (2012). He won Lam Research Award in 1997 and distinguished award from Electron Devices and Materials Association in 2011 and Association of Chemical Sensing Technology in 2015. From 2016, he was elected as the president of Association of Chemical Sensing Technology.
C. S. Lai’s Selected Publications:
 Small, 10, No. 5, 989–997(2014).
 Scientific Reports 4:5893 (2014).
 Advanced Materials 27(41) (2015)
 IEEE Electron Device Letters PP(99):1-1 (2016)
 IEEE Transactions on Nanotechnology (99):1-1 (2017)
 Carbon 113:318e324 (2017)
 Scientific Reports 7:44112 (2017).
 ACS Applied Materials & Interfaces 10(24) · June 2018