Program

Wednesday, June 19

08:10 - 08:30 Registration

08:30 - 09:00 Welcome Session

09:00 - 10:00 Keynote Speaker 1

RECONFIGURABLE TECHNOLOGIES FOR QUANTUM COMPUTING

Wayne Luk, Imperial College London, UK

Chair: Jason Anderson

10:00 - 10:45 Coffee Break + Poster Session

10:45 - 12:30 Session W1: High-Level Abstraction and Optimization

Session Chair: Nuno Paulino, University of Porto

Enabling high-level parallel programming on multi-FPGA clusters

Juan Miguel de Haro Ruiz, Carlos Ávarez Martínez, Daniel Jiménez-González and Xavier Martorell Bofill

BraggHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Maksim Levental, Arham Khan, Ryan Chard, Kazutomo Yoshii, Kyle Chard, and Ian Foster

High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares

Gento Hiruma, Mingyu Yang, Yang Li, Kazuo Sakiyama, and Yuko Hara-Azumi

Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs

Ce Guo, Haoran Wu, and Wayne Luk

12:30 - 14:00 Lunch

14:00 - 15:00 Keynote Speaker 2

A NEW COMPILER-DEVELOPMENT DISCIPLINE: APPLICATION-SPECIFIC CODE GENERATION FOR ACCELERATORS

José Nelson Amaral, University of Alberta, Canada

Chair: Lana Josipovic

15:00 - 15:40 Session W2: PhD Forum and Poster Pitches

Session Chair: João Bispo, University of Porto

PhD Forum: Implementation and analysis of custom instructions on RISC-V for Edge-AI applications

Ajay Kumar M, Vineet Kumar, Deepu John, and Shreejith Shanker

PhD Forum: MLIR-Based Homomorphic Encryption Compiler for GPU

Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, and Hideki Takase

Poster: Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures

Elias Barbudo, Thierry Grandpierre and Eva Dokladalova

Poster: An End-to-End Programming Model for AI Engine Architectures

Maksim Levental, Arham Khan, Ryan Chard, Kyle Chard, Stephen Neuendorffer and Ian Foster

15:40 - 16:10 Coffee Break + Poster Session

16:10 - 17:25 Session W3: Application I

Session Chair: Pedro Pinto, University of Porto

Embedded Security Accelerators within Network-on-Chip Environments

Julian Haase, Nico Volkens, and Diana Goehringer

Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap

Martin Langhammer, and George Constantinides

Accelerated Spiking Convolutional Neural Networks for Scalable Population Genomics

Federico Corradi, Zhanbo Shen, Hanqing Zhao, and Nikolaos Alachiotis

17:25 - 18:45 Welcome Reception

Thursday, June 20

08:30 - 08:50 Registration

08:50 - 09:00 Announcements

09:00 - 10:00 Keynote Speaker 3

ADAPTIVE COMPUTING SYSTEMS FOR AUTONOMOUS ROBOTS

Diana Göhringer, TU Dresden, Germany

Chair: Gabriel Falcão

10:00 - 10:45 Coffee Break + Poster Session

10:45 - 12:30 Session T1: Architecture and CAD

Session Chair: Shreejith Shanker, Trinity College Dublin

LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures

Raveena Raikar and Dirk Stroobandt

VIPER: A VTR Interface for Placement with Error Resilience

Kate Thurmer, and Vaughn Betz

CAD Techniques for NoC-Connected Multi-CGRA Systems

Haoran Wei, Omkar Bhilare, Hamas Waqar, and Jason Anderson

Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance

Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, and Yoshiki Yamaguchi

12:30 - 14:00 Lunch

14:00 - 15:00 Keynote Speaker 4

RECONFIGURABLE COMPUTING FOR SOFTWARE PROGRAMMERS?

Paolo Ienne, EPFL, Switzerland

Chair: Martin Langhammer

15:00 - 15:40 Session T2: Application II

Session Chair: Federico Corradi, Eindhoven University of Technology

A data compressor for FPGA-based state vector quantum simulators

Kaijie Wei, Hideharu Amano, Ryohei Niwase and Yoshiki Yamaguchi

Learned Index Acceleration with FPGAs: A SMART Approach

Geetesh More, Suprio Ray, and Kenneth B. Kent

A Hardware Solver for Simultaneous Linear Equations with Multistage Interconnection Network

Rikuya Tomii, and Tetsu Narumi

15:40 - 16:10 Coffee Break + Poster Session

16:20 - Bus to Porto Downtown

17:15 - 18:00 Visit to Port Wine Cellar "Caves Cálem"

18:00 - 19:40 Walking trip

19:40 - 22:30 Dinner at "Vinum" Restaurant (Grahams wine cellars)

22:30 Return by bus to FEUP

Friday, June 21

08:30 - 08:50 Registration

08:50 - 09:00 Announcements

09:00 - 10:00 Keynote Speaker 5

HIGHLY EFFICIENT ACCELERATION AND RECONFIGURATION FOR COMPUTING ON ENCRYPTED DATA (COED)

Ingrid Verbauwhede, KU Leuven, Belgium

Chair: Pedro Diniz

10:00 - 10:30 Coffee Break + Poster Session

10:30 - 12:30 Tutorials (part I):

[B034] Tutorial on "Developing HPC applications with OpenMP and Task-Aware MPI (TAMPI)"

Kevin Sala, and Xavier Teruel, BSC, Barcelona, Spain

[B033] Tutorial on "Memory-Centric Computing Systems"

Geraldo F. Oliveira, Onur Mutlu, Mohammad Sadrosadati, Ataberk Olgun, ETH, Zurich, Switzerland

12:30 - 14:00 Lunch

14:00 - 15:30 Tutorials (part II)

[B034] Tutorial on "Developing HPC applications with OpenMP and Task-Aware MPI (TAMPI)"

Kevin Sala, and Xavier Teruel, BSC, Barcelona, Spain

[B033] Tutorial on "Memory-Centric Computing Systems"

Geraldo F. Oliveira, Onur Mutlu, Mohammad Sadrosadati, Ataberk Olgun, ETH, Zurich, Switzerland

15:30 - 15:45 [B033] Closing Session

Wednesday to Friday, June 19-21

Poster Presentations

Poster Session: Wednesday to Friday, July 19-21: 10:00 - 10:45

Session Chairs: Tiago Santos and Luís Sousa, University of Porto

PhD Forum: Implementation and analysis of custom instructions on RISC-V for Edge-AI applications

Ajay Kumar M, Vineet Kumar, Deepu John, and Shreejith Shanker

PhD Forum: MLIR-Based Homomorphic Encryption Compiler for GPU

Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, and Hideki Takase

Poster: Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures

Elias Barbudo, Thierry Grandpierre, and Eva Dokladalova.

Poster: An End-to-End Programming Model for AI Engine Architectures

Maksim Levental, Arham Khan, Ryan Chard, Kyle Chard, Stephen Neuendorffer, and Ian Foster