KeynoteS

The proliferation of application-specific programming languages and programming frameworks, along with the use of high-efficiency accelerators, has led to the emergence of new challenges and opportunities for compiler development. In many domains, compiler writers are now tasked with creating efficient code for a small set of critical applications. In some cases values that were symbols in traditional compilers are now constants -- pe. loop bounds, model parameters, tensor shapes.

Similarly, the code generation often needs to target hardware accelerators with constrained acceleration units with fixed sizes. In some of these tasks, the construction of a compiler is more akin to the building of specialized libraries. These changes in the compilation landscape requires different skills and techniques from compiler developers in comparison with traditional compilation from general-purpose languages to general-purpose processors. 

Many domains require these specializations, including machine learning, ray-tracing graphics pipelines, tensor cores, and quantum computing. There is also opportunities to integrate automated learning tools and advanced searching in the code generation process. However, the traditional testing methodology also has to adapt to the use of such tools. This talk will argue that the training of compiler developers, and the practice of compiler development, must adapt to these changes.

The acquisitions of Altera by Intel in 2015 and of Xilinx by AMD in 2022 seem to mark a new era for field-programmable gate-arrays, or FPGAs: from a reconfigurable device mostly dedicated to prototyping and moderate-volume embedded applications, they may have a chance to become ubiquitous high-performance computing devices, alongside CPUs, GPUs, and TPUs.  Yet, one of the fundamental conditions for the adoption of any new device in a computing environment is the availability of a suitable programming paradigm. Alas, enabling software developers to apply their skills to FPGAs has been a long and, as of yet, unreached research objective in reconfigurable computing. 

In this talk, we will first discuss our experiences with the daunting task of running efficiently kernels of software-oriented imperative code on FPGAs--a seemingly simple goal which has remained elusive for a long time. We will also touch on the necessity of developing software environments to support forms of explicit parallelism profitable to FPGAs. We will argue that without progress on these fronts, reconfigurable computing will remain a missed opportunity.

Quantum computing offers a completely new foundation for next-generation computer systems. However, quantum computers are much less accessible compared to classical computer systems based on silicon.

This talk explores how reconfigurable computing can contribute to the development of quantum computers. In particular, it describes an approach for efficient simulation of quantum circuits based on reconfigurable technologies, which involves a pipelined dataflow architecture targeting a compact circuit representation format. A data decoupling method is adopted to partition computing tasks and data into non-interacting subsets, significantly reducing off-chip interaction overhead. The proposed approach shows promise in enhancing performance and energy efficiency for quantum computer simulation, and its extension to support heterogeneous cloud systems with quantum computing capability will be presented.