MEMBER

Dongyun Kam, Ph.D.

Postdoc Researcher,

School of Electrical Engineering,

Korea Advanced Institute of Science and Technology (KAIST)

Contact Information

• Address : #4219, Information & Electronics Building (E3-2), KAIST, Daejeon, Korea

• Email : rkaehddbs[at]postech.ac.kr

• Office : +82-(0)42-350-7579

Educational Backgrounds

• [2020/09~2024/08] Ph.D. in Electrical Engineering, POSTECH, Pohang, Korea

• [2018/09~2020/08] M.S. in Electrical Engineering, POSTECH, Pohang, Korea 

• [2014/03~2018/08] B.S. in Electrical Engineering, POSTECH, Pohang, Korea

Professional Experiences

• [2025/08~Present] Postdoc Researcher, Sch. Electrical Engineering, KAIST, Daejeon, Korea

• [2025/03~2025/08] Visiting Researcher, Sch. Electrical Engineering, KAIST, Daejoen, Korea

• [2024/08~2025/08] Postdoc Researcher, Dept. Electrical Engineering, POSTECH, Pohang, Korea

• [2023/03~2023/09] Visiting Researcher, Dept. EECS, University of Michigan, Ann Arbor, USA

• [2018/01~2024/08] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea

• [2017/01~2017/06] Internship, Alticast, Seoul, Korea

Research Interests

• Acceleration of Deep Neural Network Inferences

• Error Correction Code (ECC) for mobile systems

• 5G Communication systems

• ASIC/FPGA Implementation

Publications

• International Journal Papers

  1. Jaehee Kim, Changhyeon Kim, Sangbu Yun, Dongyun Kam, Soonhyun Kwon, Yongjune Kim, and Youngjoo Lee*, "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 11, pp. 6528-6540, Nov. 2025. (Invited)

  2. Sunwoo Yoo, Seungwoo Hong, Dongyun Kam, and Youngjoo Lee*, "A lightweight ML-based ECG classification system using self-personalized anomaly detector," IEEE Journal of Biomedical and Health Informatics, vol. 29, no. 10, pp. 7274-7284, Oct. 2025.

  3. Jaehee Kim+, Sangil Han+, Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "A design framework for cost-efficient sorters with arbitrary input/output constraints," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 12, pp. 5410-5419, Dec. 2024. (Invited)

  4. Dain Park, Dongyun Kam, Sangbu Yun, Jeongwon Choe, and Youngjoo Lee*, "Hard-decision SCL polar decoder with weighted pruning operation for storage applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 9, pp. 4181-4185, Sep. 2024.

  5. Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "Low-latency SCL polar decoder architecture using overlapped pruning operations," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1417-1427, Mar. 2023.

  6. Changhyeon Kim, Dongyun Kam, Seokki Kim, Giyoon Park, and Youngjoo Lee*, "Simplified ordered statistic decoding for short-length linear block codes," IEEE Communications Letters, vol. 26, no. 8, pp. 1720-1724, Aug. 2022.

  7. Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, and Youngjoo Lee*, "Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, pp. 1774-1787, Apr. 2022.

  8. Dongyun Kam, Hoyoung Yoo, and Youngjoo Lee*, "Ultra-low-latency successive cancellation polar decoding architecture using tree-level parallelism," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 6, pp. 1083-1094, June 2021.

  9. Seokha Hwang, Seungsik Moon, Dongyun Kam, Inn-Yeol Oh, and Youngjoo Lee*, "High-throughput and low-latency digital baseband architecture for energy-efficient wireless VR systems," MDPI Electronics, vol. 8, no. 7:815, pp. 1-13, July 2019.

  10. Seungsik Moon, In-Soo Kim, Dongyun Kam, Dong-Woo Jee, Junil Choi*, and Youngjoo Lee*, "Massive MIMO systems with low-resolution ADCs: Baseband energy consumption vs. Symbol detection performance," IEEE Access, vol. 7, no. 1, pp. 6650-6660, Jan. 2019.

• International Conference Proceedings

  1. Jaehee Kim, Changhyeon Kim, Sangbu Yun, Dongyun Kam, Soonhyun Kwon, Yongjune Kim, and Youngjoo Lee*, "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation," IEEE International Symposium on Integrated Circuits and Systems (ISICAS, TCAS-I Special Issue), Qingdao, China, Oct. 2025.

  2. Seungwoo Hong, Jung Gyu Min, Jin Hyun, Jaehee Kim, Dongyun Kam, Eunji Yoo, Pilsu Kim, Jaehyung Yoo, Hyoung-Euk Lee, and Youngjoo Lee*, "FPGA-based real-time ISP accelerator using low-cost line buffers and non-linear functions," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Busan, Korea, Oct. 2025.

  3. Junehyuk Oh, Soonhyun Kwon, Dongyun Kam, and Youngjoo Lee*, "On the hardware efficiency of short-length polarization-adjusted convolutional polar decoders," IEEE Asia Pacific Conference of Circuits and Systems (APCCAS), Busan, Korea, Oct. 2025.

  4. Dongyun Kam, Myeongji Yun, Sunwoo Yoo, Seungwoo Hong, Zhengya Zhang, and Youngjoo Lee*, "Panacea: Novel DNN accelerator using accuracy-preserving asymmetric quantization and energy-saving bit-slice sparsity," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, NV, USA, Mar. 2025.

  5. Sangil Han+, Jaehee Kim+, Dongyun Kam, Byeong Yong Kong, Mijung Kim, Young-Seok Kim, and Youngjoo Lee*, "Constrained sorter design using zero-one principle," IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, May 2024.

  6. Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, and Youngjoo Lee*, "A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.

  7. Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, and Youngjoo Lee*, "Energy-efficient RISC-V-based vector processor for cache-aware structurally-pruned transformers," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, Aug. 2023.

  8. Ranggi Hwang, Minhoo Kang, Jiwon Lee, Dongyun Kam, Youngjoo Lee, and Minsoo Rhu*, "GROW: A row-stational sparse-dense GEMM accelerator for memory-efficient graph convolutional neural networks," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Montreal, QC, Canada, Feb. 2023.

  9. Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology," IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, June 2022.

  10. Dongyun Kam+, Jung Gyu Min+, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, and Youngjoo Lee*, "Design and evaluation frameworks for advanced RISC-based ternary processor," IEEE/ACM Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Mar. 2022.

  11. Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, and Youngjoo Lee*, "FPGA-based ordered statistic decoding architecture for B5G/6G URLLC IIOT networks," IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Nov. 2021.

  12. Dongyun Kam, Byeong Yong Kong, and Youngjoo Lee*, "Low-latency polar decoder using overlapped SCL processing," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Toronto, Canada, Jun. 2021, pp. 4860-4864.

  13. Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, and Youngjoo Lee*, "Ultra-low-latency LDPC decoding architecture using reweighted offset min-sum algorithm," IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, Oct. 2020, pp. 1-5. 

  14. Dongyun Kam and Youngjoo Lee*, "Ultra-low-latency parallel SC polar decoding architecture for 5G wireless communications," IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-5. (Student Travel Grant Award)

• Domestic Conference Proceedings

  1. 감동윤, 이영주*, "Complexity-latency tradeoff for 5G SCL polar decoder architecture," 제 29회 한국반도체학술대회, Jan. 2022.

  2. 김창현, 감동윤, 박기윤, 김석기, 이영주*, "짧은 오류정정부호를 위한 OSD 알고리즘의 복잡도 분석," 대한전자공학회 하계종합학술대회, Aug. 2020. (네이버 논문상)

  3. 감동윤, 이영주*, "Performance analysis and optimization of low-latency SC polar decoder," 2019년도 한국통신학회 동계종합학술발표회, Jan. 2019, pp. 334-335.

  4. 문승식, 김인수, 감동윤, 지동우, 최준일, 이영주, "Masive MIMO 시스템을 위한 통합 심볼 검출기 설계," 제 1회 반도체공학회 학술대회, Dec. 2018.

• Patents

  1. Jemin Lee, Youngjoo Lee, and Dongyun Kam, "Multi-bit partial sum network device for parallel SC decoder," PCT/KR2019/017108.

  2. Jemin Lee, Youngjoo Lee, and Dongyun Kam, "Polar codes decoding device and method thereof," PCT/KR2019/015834.

  3. 이제민, 이영주, 감동윤, "병렬 SC 복호기의 멀티비트 부분합 네트워크 장치," 등록번호: 10-2170785, 출원번호: 10-2019-0077704.

  4. 이제민, 이영주, 감동윤, "극부호 복호 장치 및 방법," 등록번호: 10-2115216, 등록번호: 10-2115216, 출원번호: 10-2019-0077703.

  5. 이영주, 감동윤, "통신 시스템에서 폴라 코드에 기초한 디코딩 방법 및 장치," 등록번호: 10-2144266, 출원번호: 10-2019-0054843.

Awards and Honors

• Best Paper Award, Samsung-Postech Research Center, 2024.

• Post-Doc. Fellowship "POSTECH Initiative for fostering Unicorn of Research & Innovation (PIURI)", 2024.

• POSTECHIAN Fellowship, 2024.

• IEEE SSCS Seoul Chapter Award (Best Design Award), International SoC Design Conference (ISOCC), 2020.

• Special Award (기업특별상), 21st Korea Semiconductor Design Contest, 2020.

• Best Paper Award (네이버 논문상), Summer Annual Conference of IEIE, 2020.

• Student Travel Grant Award, IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

• Encouragement Award (장려상), 25th Samsung Humantech Paper Award, 2019.