News
2024
[2024/07] Our research on the ML-based MIMO detector has received the Best Design Award at the 2024 IDEC Congress Chip Design Contest.
[2024/06] Our paper entitled "A design framework for cost-efficient sorters with arbitrary input/output constraints," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2024/05] Our paper entitled "Cost-efficient partially-parallel LDPC decoder architecture for 50G-PON standard," has been accepted for presentation at the 21st International SoC Design Conference (ISOCC 2024).
[2024/05] Jaehee has received the Student Travel Grants by IEEE CASS for his paper "Constrained sorter design using zero-one principle" at IEEE ISCAS 2024.
[2024/04] Our paper entitled "A 43.9 μs IRS controller SoC with grid-based phase-shift optimization in 28 nm CMOS technology for next-generation communication," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2024/04] Our paper entitled "A dual-precision and low-power CNN inference engine using a heterogeneous processing-in-memory architecture," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2024/04] Dongyun has received the POSTECHIAN Fellowship by POSTECH EE.
[2024/03] Our paper entitled "Hard-decision SCL polar decoder with weighted pruning operation for storage applications," has been accepted for publication in the IEEE Transactions on Circuits and Systems II: Express Briefs.
[2024/02] Our paper entitled "Partially-structured transformer pruning with patch-limited XOR-gate compression for stall-free sparse-model access," has been accepted for presentation at the 61st Design Automation Conference (DAC 2024).
[2024/02] Hyunhoon has received the Student Travel Grant Award by IEEE ISSCC 2024.
[2024/02] Seungsik has received the Best PhD Thesis Award by POSTECH EE.
[2024/02] Eunji has received the Best MS Thesis Award by POSTECH EE.
[2024/01] Our paper entitled "Multi-group multicasting systems using multiple RISs," has been accepted for publication in the IEEE Transactions on Wireless Communications.
[2024/01] Our paper entitled "LUT-GEMM: Quantized matrix multiplication based on LUTs for efficient inference in large-scale generative language models," has been accepted for presentation at the 12th International Conference on Learning Representations (ICLR 2024).
[2024/01] Our paper entitled "Low-power encoder and compressor design for approximate radix-8 Booth multiplier," has been accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS 2024).
[2024/01] Our paper entitled "Constrained sorter design using zero-one principle," has been accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS 2024).
[2024/01] Our paper entitled "Cost-efficient SIMD ASIP architecture for mobile touchscreen controllers," has been accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS 2024).
2023
[2023/12] Our paper entitled "Intelligent MIMO detection with momentum-induced unfolded layers," has been accepted for publication in the IEEE Wireless Communications Letters.
[2023/12] Our research on the storage-aware non-binary LDPC decoder design has received the Best Paper Award at the 2023 Annual Conference of ISE.
[2023/10] Our paper entitled "A 2.7~13.3 uJ/boot/slot flexible RNS-CKKS processor in 28nm CMOS technology for FHE-based privacy-preserving computing," has been accepted for presentation at the IEEE International Solid-State Circuits Conference (ISSCC 2024).
[2023/10] Our paper entitled "A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications," has been accepted for presentation at the IEEE International Solid-State Circuits Conference (ISSCC 2024).
[2023/09] Our paper entitled "Optimizations of privacy-preserving DNN for low-latency inference on encrypted data," has been accepted for publication in the IEEE Access.
[2023/09] Our paper entitled "Block orthogonal sparse superposition codes for ultra-reliable low-latency communications," has been accepted for publication in the IEEE Transactions on Communications.
[2023/08] Our paper entitled "Analysis of deep learning-based MIMO detectors," has been accepted for presentation at the 14th International Conferenc on ICT Convergence (ICTC 2023).
[2023/08] Our research on the low-complexity non-binary LDPC decoder architecture for storage applications has received the Excellence Paper Award by the Samsung-POSTECH Research Center.
[2023/08] Our paper entitled "Low-complexity phase shift design for IRS-aided SU-MIMO wireless systems," has been accepted for presentation at the 20th International SoC Design Conference (ISOCC 2023).
[2023/08] Our research on the area-efficient 4KB 0.9-rate NB-LDPC decoder has received the Excellence Design Award at the 2023 POSTECH BMSC Chip Design Contest.
[2023/07] Our paper entitled "Cost-efficient GPIP processing for large-scale multi-user MIMO systems," has been accepted for publication in the IEEE Access.
[2023/05] Our paper entitled "Energy-efficient RISC-V-based vector processor for cache-aware structurally-pruned transformers," has been accepted for presentation at the 2023 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2023).
[2023/04] Our paper entitled "A scalable precoding processor for large-scale MU-MIMO systems," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2023/03] Our paper entitled "A 2.35 Gb/s/mm^2 (7440, 6696) NB-LDPC decoder over GF(32) using memory-reduced column-wise trellis min-max algorithm in 28nm CMOS technology," has been accepted for presentation at the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI 2023).
[2023/02] Our paper entitled "TF-MVP: Novel sparsity-aware transformer accelerator with mixed-length vector pruning," has been accepted for presentation at the 60th Design Automation Conference (DAC 2023).
[2023/02] Our paper entitled "Sparsity-aware memory interface architecture using stacked XORNet compression for accelerating pruned-DNN models," has been accepted for presentation at the 6th Conference on Machine Learning and Systems (MLSys23).
2022
[2022/12] Our paper entitled "Low-latency SCL polar decoder architecture using overlapped pruning operations," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2022/10] Our paper entitled "An automated synthesis framework for fast evaluation of maximum operating frequency," has been accepted for presentation at the 22nd International Conference on Electronics, Information, and Communication (ICEIC 2023).
[2022/10] Our research on the channel estimation of IRS-aided MIMO systems has been received the ETRI Award at the 19th International SoC Design Conference (ISOCC 2022).
[2022/10] Our paper entitled "Simplified compressor and encoder designs for low-cost approximate radix-4 Booth multiplier," has been accepted for publication in the IEEE Transactions on Circuits and Systems II: Express Briefs.
[2022/10] Our paper entitled "GROW: A row-stational sparse-dense GEMM accelerator for memory-efficient graph convolutional neural networks," has been accepted for presentation at the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2023).
[2022/09] Our research on the ML-based tumor microenvironment analysis has received the SK Telecom Award (one of top 10 ideas) at the ICT Challenge 2022.
[2022/08] Our paper entitled "Hardware analysis of channel estimation method for IRS-aided MIMO wireless systems," has been accepted for presentation at the 19th International SoC Design Conference (ISOCC 2022).
[2022/08] Our paper entitled "Fast estimation of NTT/INTT accelerator costs for RNS-based homomorphic encryption," has been accepted for presentation at the 19th International SoC Design Conference (ISOCC 2022).
[2022/08] Our Ph.D. student Seungsik Moon has been selected as a recipient of IEEE CASS Pre-Doctoral Grants.
[2022/07] Our research on the high-performance MU-MIMO processor has received the Excellence Design Award at the 2022 IDEC Congress Chip Design Contest.
[2022/07] Our research on the high-speed LDPC decoder architecture has received the Excellence Poster Award at the 2022 IDEC Congress Chip Design Contest.
[2022/05] Our paper entitled "High-throughput non-binary LDPC decoder architecture using parallel EMS algorithm," has been accepted for publication in the IEEE Journal of Solid-State Circuits.
[2022/05] Our paper entitled "Simplified ordered statistic decoding for short-length linear block codes," has been accepted for publication in the IEEE Communications Letters.
[2022/05] Our paper entitled "CHAMP: Channel merging process for cost-efficient highly-pruned CNN acceleration," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2022/04] Our paper entitled "A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology," has been accepted for presentation at the 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI 2022).
[2022/03] Our paper entitled "A study on reliable high-speed HBC enhanced by ECC for wearable neural interfaces," has been accepted for presentation at the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2022).
[2022/03] Our paper entitled "Lightweight end-to-end stress recognition using binarized CNN-LSTM models," has been accepted for presentation at the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2022).
[2022/02] Our paper entitled "Low-complexity beamforming optimization for IRS-aided MU-MIMO wireless systems," has been accepted for publication in the IEEE Transactions on Vehicular Technology.
[2022/01] Our paper entitled "Algorithm-hardware co-optimization for cost-efficient ML-based ISP accelerator," has been accepted for presentation at the 2022 IEEE International Symposium on Circuits and Systems (ISCAS 2022).
[2022/01] Our paper entitled "A 2.86Gb/s fully-flexible MU-MIMO processor for jointly optimizing user selection, power allocation, and precoding in 28nm CMOS technology," has been accepted for presentation at the 2022 IEEE Custom Integrated Circuits Conference (CICC 2022).
[2022/01] Our paper entitled "Convolutional neural networks with discrete cosine transform features," has been accepted for publication in the IEEE Transactions on Computers.
2021
[2021/12] Our paper entitled "Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2021/11] Our research on the low-latency OSD hardware for IIoT networks has received the Bronze Medal (특허청장상) at the 22nd Korea Semiconductor Design Contest.
[2021/11] Our paper entitled "Design and evaluation frameworks for advanced RISC-based ternary processor," has been accepted for presentation at IEEE/ACM Design, Automation and Test in Europe Conference (DATE 2022).
[2021/10] Our research on the low-complexity DNN-based voice activity recognition has received the Best Paper Award (IEEE CASS Daegu Chapter Award) at the 18th International SoC Design Conference (ISOCC 2021).
[2021/10] Our paper entitled "Performance evaluation of systolic DCNN accelerators," has been accepted for presentation at the 6th International Conference on Consumer Electrocins Asia (ICCE-Asia 2021).
[2021/09] Our research on the low-latency error-corrcting circuits for emerging non-volatile memory has received the Best Paper Award by the Samsung-POSTECH Research Center.
[2021/09] Our paper entitled "Area- and energy-efficient LDPC decoder using mixed-resolution check-node processing," has been accepted for publication in the IEEE Transactions on Circuits and Systems II: Express Briefs.
[2021/08] Our paper entitled "Low-complexity voice activity detection algorithm for edge-level device," has been accepted for presentation at the 18th International SoC Design Conference (ISOCC 2021).
[2021/08] Our paper entitled "Low-complexity on-device ECG classifier using binarized neural network," has been accepted for presentation at the 18th International SoC Design Conference (ISOCC 2021).
[2021/08] Our paper entitled "A 7Gbps (160, 80) non-binary LDPC decoder with dual-message EMS algorithm in 22nm FinFET techonology," has been accepted for presentation at the 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC 2021).
[2021/08] Our paper entitled "FPGA-based ordered statistic decoding architecture for B5G/6G URLLC IIOT networks," has been accepted for presentation at the 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC 2021).
[2021/07] Our research on the on-device channel generation has received the Excellence Paper Award at the 2021 Summer Annual Conference of ISE.
[2021/07] Our paper entitled "Utilizing energy-quality trade-off for low-cost ML-based compressive sensing reconstruction," has been accepted for presentation at the 55th Asilomar Conference on Signals, Systems and Computers (ACSSC 2021).
[2021/07] Our Research on the approximate multiplier design for low-power DCNN processing has received the Best Paper Award (네이버 논문상) at the 2021 Summer Annual Conference of IEIE.
[2021/06] Prof. Lee has received the Excellence Award (우수참여교수상) by IC Design Education Center (IDEC).
[2021/06] Our paper entitled "Low-cost network scheduling of 3D-CNN processing for embedded action recognition," has been accepted for publication in IEEE Access.
[2021/05] Seungsik has received the POSTECHIAN Fellowship by POSTECH EE.
[2021/04] Our paper entitled "Design and analysis of approximate compressors for balanced error accumulation in MAC operator," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2021/03] Our paper entitled "Energy-efficient intelligent EPTS device using novel DCNN-based dynamic sensor activation," has been accepted for presentation at the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2021).
[2021/03] Our paper entitled "Ultra-low-latency successive cancellation polar decoding architecture using tree-level parallelism," has been accepted for publication in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2021/01] Our paper entitled "Low-latency polar decoder using overlapped SCL processing," has been accepted for presentation at IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2021).
[2021/01] Our paper entitled "Rapid design space exploration of near-optimal memory-reduced DCNN architecture using multiple model compression techniques," has been accepted for presentation at IEEE International Symposium on Circuits and Systems (ISCAS 2021).
2020
[2020/11] Our paper entitled "Approach to improve the performance using bit-level sparsity in neural networks," has been accepted for presentation at IEEE/ACM Design, Automation and Test in Europe (DATE 2021).
[2020/11] Our paper entitled "Approximate LSTM computing for energy-efficient speech recognition," has been accepted for publication in MDPI Electronics.
[2020/11] Our reseach on the high-performance lane detection algorithm has received the most excellence industry/university coopration award (해동 산학최우수논문상) by IEIE Korea.
[2020/10] Our research on the low-latency polar decoder architecture has received the IEEE SSCS Seoul Chapter Award (Best Design Award) at the 17th International SoC Design Conference (ISOCC 2020).
[2020/10] Our paper entitled "Energy-efficient wearable EPTS device using on-device DCNN processing for football activity classification," has been accepted for publication in MDPI Sensors.
[2020/10] Our research on the noise-resilient on-device CNN accelerator has received the Special Award (기업특별상) at the 21st Korea Semiconductor Design Contest.
[2020/08] Our research on the hardware-aware OSD algorithm for short-length error-correction codes has received the Best Paper Award (네이버 논문상) at the 2020 Summer Annual Conference of IEIE.
[2020/08] Our paper entitled "Energy-efficient precoding architecture for multi-user MIMO systems," has been accepted for presentation at the 54th Asilomar Conference on Signals, Systems, and Computers (ACSSC 2020).
[2020/08] Our paper entitled "Hierarchical approximate memory for deep neural network applications," has been accepted for presentation at the 54th Asilomar Conference on Signals, Systems and Computers (ACSSC 2020).
[2020/08] Our paper entitled "Low-complexity DNN-based end-to-end automatic speech recognition using low-rank approximation," has been accepted for presentation at the 17th International SoC Design Conference (ISOCC 2020).
[2020/08] Our paper entitled "High-quality HTTP live streaming system for limited communication bandwidth," has been accepted for presentation at the 17th International SoC Design Conference (ISOCC 2020).
[2020/04] Our paper entitled "Layerwise buffer voltage scaling for energy-efficient convolutional neural network," has been accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2020/02] Seungsik has received the Best MS Thesis Award by POSTECH EE.
[2020/02] Our research on the unified AES/Hash accelerator for physical layer security has received the Best Poster Award at the 27th Korean Conference on Semiconductors (KCS).
[2020/02] Our paper entitled "Low-latency unfolded-KES architecture for emerging storage class memories," has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.
[2020/01] Our paper entitled "Ultra-low-latency LDPC decoding architecture using reweighted offset min-sum algorithm," has been accepted for presentation at the 2020 IEEE International Symposium on Circuits and Systems (ISCAS 2020).
[2020/01] EPIC LAB has been re-established by Prof. Youngjoo Lee. Now, we re-start to write our EPIC story.