Lab 5: DAC Siren

Purpose

This lab centralizes around understanding how to utilize a digital to analog converter (DAC), particularly for generating a wailing audio siren. To accomplish this, digital audio sequences will need to be formatted into a serial stream to drive a Pmod I2S2 stereo audio input and output device.

Digital to Analog

Digital signals, which have been our primary focus with the sole exception of lab 3 when working with our VGA interface, are ones that have two states. These are high, or '1', and low, or '0'. To create a simplified analogy, a value of '1' would be read by an input pin if the voltage the external source is providing is closer to the maximum voltage than the minimum (generally 0). When dealing with computing the signals are often fired off at insanely quick rates, meaning a signal may not always reach the full maximum voltage, and must therefore be assumed so long as it reaches above a threshold voltage.

Analog signals are any value from the minimum to the maximum. We can think of them as continuous values, where as digital are discrete.

DAC Interface

To interact with the Pmod interface of the digilent I2S2 shown below, we must first understand each of the pins provided. Worth noting, this Pmod features both audio in and audio out jacks, but we will only deal with the 6 pins associated with the audio out for simplicity.

The six pins we will be taking a look at are outlined in the Digilent reference manual for this Pmod, which can be found here. If you do not understand the general Pmod pinout procedure, please refer to lab 4.

Pin 1 is for the Master Clock, abbreviated as MCLK. This is a high speed clock which drives the on-chip oversampled delta-sigma modulator. I know, that's a mouthful. For our sake, the master clock indicates the fastest possible rate any of the other interfaces will run at. It also ensures the synchronization of the different clocks we will discuss in a moment.

Pin 2 is the Left-Right Clock, often referred to as LRCK or the Word Select Clock. This clock indicates whether a particular set of data is intended to be send through the left or right audio channel. Depending on whether the LRCK is low or high indicates which channel to transfer data through.

Pin 3 is the Serial Clock, called SCLK or Bit Clock. This one transfers our internally generated data to the DAC. The transfer itself occurs on the rising edge of the SCLK for the sake of this project. As each channel utilizes 16-bits of data here, the SCLK runs at 32x the sampling clock.

Finally, pin 4 is the Serial Data Input pin (SDIN), which reads in the serial data that the SCLK sends to the DAC.

Pins 5 and 6 are reserved for power, as is true with all Digilent Pmods.

To fully understand how most of these pins interact, we can look to the diagram above. The LRCK alternates between the two channels discretely. The SCLK sends data from the SDIN with each rising clock edge, and the SDIN is a continuous stream of bit data.

Demonstration

Below is a video demonstration of the lab without any modifications.