What is a half-adder?

A half-adder is a group of logic gates that implement basic boolean logic. Half-adders act as the foundation for arithmetic logic units (ALUs) within CPUs to perform advanced arithmetic operations on operands. The logic within a half-adder results in bit patterns that equate to perform basic addition on two binary numbers.

Looking at all of the cases for two binary inputs, the result of 0 + 0 is 0, 1 + 0 is 1, and 0 + 1 is also 1. In these cases, the output bit or result is referred to as the sum. However, when we go to consider the case of 1 + 1, there is an overflow and we must perform a carry operation. Here, the second output of a half-adder called the carry comes into play. Below is the truth table for a half-adder.

The Underlying Logic

This truth table is all well and good, but how do we implement this into the FPGA? To do this we can translate the results of sum and carry into boolean expressions.

Notice that sum is only true when either A or B are true, but not both. This is representative of an XOR gate, which is the circuit element we will use to recreate a half-adder later. Here, we can say sum is represented by A XOR B.

The only case where carry is true is when both A and B are true. This makes the carry a very simple case to handle, as it can merely be represented by A AND B.

Knowing this, the schematic below depicts how the logic gates will be implemented in our circuit.

FPGA Implementation

Now that you understand the half-adder from the ground up, we can implement all of this onto our FPGA board. The VHDL source file for a half-adder can be found on my GitHub here.

TO INCLUDE: Demonstration Video