What is a full-adder?

A full-adder is an extension of the half-adder we just created. It allows us to include the carry from a previous adder, effectively outputting bit patterns that reflect addition of up to three binary numbers at once. Full-adders can comprise of two half-adders stitched together or they can be built from the ground up.

When chained together, full-adders allow for significantly more complex arithmetic to be performed within the ALU. Below is the full truth table for a full-adder.

The Underlying Logic 2: Electric Boogaloo

This truth table still seems relatively simple. The only difference is we now have a third input, called Cin for Carry in. This third input allows us to explore the full range of sum and Cout (carry out) options. Unlike before, now both sum and Cout can be true at the same time.

Though the input is simple, trying to determine the boolean expressions that represent the outputs is a little more complex.

Now, we can represent sum with the expression A XOR B XOR Cin. Looking at the four cases where sum is true, they are only where 1 or 3 input values are true. By XORing all three inputs, the value of sum will never be true when only two of the inputs are true. Take the case of A = 1, B = 1, Cin = 0 for example. A XOR B will be 0, and then (A XOR B) XOR Cin would be equivalent to 0 XOR 0, which would always be 0.

Here Cout is true when at least two of the inputs are true. To represent this, we can say when Cout is logically equivalent to (A AND B) OR (B AND Cout) OR (Cout AND A).

Slightly more complex than the half-adder, we can now represent our sum and Cout once again using logic gates.

FPGA Implementation

Similar to the half-adder, the VHDL source code can be found on my GitHub here.

TO INCLUDE: VIDEO DEMONSTRATION