#include <systemc.h>

SC_MODULE(fir) {

    sc_in< bool >           clk;

    sc_in< bool >           rst;

    sc_in< sc_int<16> >     inp;

    sc_out< sc_int<16> >    outp;

    // Coefficients for each FIR

    const sc_uint<8> coef[5] = { 18, 77, 107, 77, 18 };

    void fir_main();

    SC_CTOR(fir) {

        SC_CTHREAD(fir_main, clk.pos());

        reset_signal_is(rst, true);

    }

};

#include "fir.h"

// FIR Main thread

void fir::fir_main(void) {

    // Reset code

    sc_int<16> taps[5];

    outp.write(0);

    wait();

    while (true) {

        for (int i = 4; i > 0; i--) {

            taps[i] = taps[i - 1];

        }

        // Read inputs

        taps[0] = inp.read();

        // Algorithm code

        sc_int<16> val;

        for (int i = 0; i < 4; i++) {

            val += coef[i] * taps[i];

        }

        // Write outputs

        outp.write(val);

        wait();

    }

}

#include <systemc.h>

SC_MODULE(tb) {

    sc_in< bool >           clk;

    sc_out< bool >          rst;

    sc_in< sc_int<16> >     outp;

    sc_out< sc_int<16> >    inp;

    void source();

    void sink();

    SC_CTOR(tb) {

        SC_CTHREAD(source, clk.pos());

        SC_CTHREAD(sink, clk.pos());

    }

};

#include "tb.h"

void tb::source() {

    // Reset

    inp.write(0);

    inp.write(1);

    wait();

    rst.write(0);

    wait();

    //…

    sc_int< 16 > tmp;

    // Send stimulus to FIR

    for (int i = 0; i < 64; i++) {

        if (i > 23 && i < 29)

            tmp = 256;

        else

            tmp = 0;

        inp.write(tmp);

        wait();

    }

}

void tb::sink() {

    sc_int< 16 > indata;

    // Read output coming from DUT

    for (int i = 0; i < 64; i++) {

        indata = outp.read();

        wait();

        cout << i << " :\t" << indata.to_int() << endl;

    }

    // End simulation

    sc_stop();

}

#include <systemc.h>

#include "fir.h"

#include "tb.h"

// Module declarations

SC_MODULE ( SYSTEM ) {

  // Local signal declarations

  tb    *tb0;

  fir   *fir0;

  sc_signal< bool >   rst_sig;

  sc_signal< sc_int<16> > inp_sig;

  sc_signal< sc_int<16> > outp_sig;

  sc_clock      clk_sig;

  SC_CTOR( SYSTEM ):clk_sig("clk_sig", 10, SC_NS) { 

    // Module instance signal connections

    tb0 = new tb( "tb0" );

    tb0 -> clk( clk_sig );

    tb0 -> rst( rst_sig );

    tb0 -> inp( inp_sig );

    tb0 -> outp( outp_sig );

    fir0 = new fir( "fir0" );

    fir0 -> clk( clk_sig );

    fir0 -> rst( rst_sig );

    fir0 -> inp( inp_sig );

    fir0 -> outp( outp_sig );

  }

  ~SYSTEM(){

    delete tb0;

    delete fir0;

  } // Destructor

};

int sc_main( int argc, char* argv[] ){

  SYSTEM *top = NULL;

  top = new SYSTEM( "top" );

  sc_start();

  return 0;

}