A fast and easy-to-debug simulation environment for AI chip designers is essential for efficient verification and optimization. Loosely timed SystemC models for an AI chip will be developed and verified against RTL designs for the AI chip.
A scalable hardware architecture of a power calculator whose area can be reasonably small is under research. The power calculator is based on a high-level power model that captures the gate-level power behavior of a design under test.
Power analysis has been one of the most undeveloped areas in electronic design automation. The extremely slow speed of power analysis software prohibits users from performing in-depth power analyses during their project period. The extremely slow speed of logic simulation has been addressed by hardware emulation technologies. Similarly, the slow speed of power analysis can be addressed by hardware emulation based approaches.
Current practices of power analysis at register transfer level (RTL) or lower are neither accurate nor fast enough for a whole system-on-chip (SoC) with real scenarios mainly due to extremely slow simulation speed. Note that practical RTL or lower level power anlaysis tehcniques obtain switching activities from simulation results with given scenarios. For example, the RTL simulation speed for an SoC of more than 10M gate count ranges from three to thirty cycles per second (cps). For simplicity, let us assume that the whole SoC is operated by a clock of 300 MHz and its simulation speed is 30 cps. Then, it takes 10 million seconds (about 115 days) to simulate a one-second of real-time scenario. As power analysis is iteratively performed for measuring the effects of power optimization, this long simulation time is not acceptable. So, for the current practices of the whole system level power analysis at RTL or lower level, each intellectual property (IP) circuit in an SoC is separately analyzed with a worst-case scenario that causes the maximum power consumption of the IP circuit. Then, arithmetic sum of power values for each IP is computed, which severely exaggerates the power consumption of the SoC with a real scenario because no real scenario makes every IP circuit in an SoC consume the maximum power.
High-level power analysis addresses these problems of low level power analysis techniques by evelating the level of design abstractions: for example, electronic system level (ESL). We are conducting an independent research on high-level power analysis composed of the following objectives:
To research on a high-level power model based on clock gating domains (patented)
To explore SoC architectures considering power consumption with the proposed high-level power models and real scenarios
To research on system level power optimization techniques
Architectures of a terminal modem system-on-a-chip (SoC) for the IEEE 802.16m has been studied using electronic system level (ESL) designs. This study is composed of the following year-by-year objectives:
To develop SystemC/C++ design for architecture exploration (1st year)
To research on a systematic design method of a large hardware block for buffer memory and interconnection optimization (1st to 2nd year)
To explore SoC architectures based on the completed standards (2nd year)
To provide register transfer level (RTL) intellectual property (IP) circuits of the IEEE 802.16m Rx-modem block (2nd year)
Computer vision based user interfaces are getting attentions as an advanced human computer interaction (HCI) technology. The realiablities and computational complexities of the algorithms are challenging problems. This study is composed of the following objectives:
To research on a robust hand gesture recognition algorithm for controlling a two dimensional menu on TV
To explore SoC architectures implementing the hand gesture recognition algorithm for a real-time user interaction
To identify and develop intellectual property (IP) circuits for such an SoC
A study on algorithms of a computer vision based user interface is proposed. We aim to develop an algorithm that recognizes hand motions with complex stationary background using relative pixel colors rather than absolute pixel colors of hands. In addition, an SoC architecture for the user interface will be proposed.
Electronic system level (ESL) simulation methodology for board-level performance analysis for multimedia applications running on multiple processor SoCs (MPSoCs) is proposed. The proposed methodology must be fast enough to simulate the board-level system behavior in minutes and must be accurate enough to compare relative performance of different chip sets including memories. Various assumptions regarding system information are necessary, which are usually available in industry. The proposed ESL approach needs to analyze performance variations of the multimedia applications due to data dependencies too.