Digital Systems Lab.
School of Semiconductor Systems Engineering
Kwangwoon University, Seoul, South Korea
School of Semiconductor Systems Engineering
Kwangwoon University, Seoul, South Korea
Computer hardware design
High level power modeling and power optimization of a very large scale integrated circuit (VLSI)
System-on-a-chip (SoC) architecture design
Design for testability
Design automation
DSL is looking for research assistant candidates all year round. A full tuition and a stipend will be supported. Two annual DSL workshops are held in summer and in winter. Junior or Senior undergraduate students can arrange a meeting with professor Yi to explore the possibilities.
We are looking for candidates with strong knowledge on the followings:
Mendatory
Computer architecture (caches, memory systems, interrupts, and so on)
Verilog or SystemVerilog
C
Courses
Digital logic circuits
Hardware description language (HDL) design
Computer architecture
Digital system design
VLSI design - logic synthesis, design for testability, static timing analysis
Preferred
VLSI front-end design flow (logic synthesis, static timing analysis, and power analysis flows)
C++
SystemC
URIs are undergraduate students who are planning to pursue the graduate study program after graduation. DSL offer URIs to participate in a research project. In addition, various group study opportunities on the related topics are provided.
For more details on the above announcements, please contact professor Yi (joonhwan.yi [at] kw.ac.kr)