Lab 1

Laboratory 1 - Seven Segment Decoder

Part 1 - LED Decoder

1. Create a new project in Vivado.
2. Create a new source file of file type VHDL and copy code from section 2.1 in Lab PDF.
3. Create a new constraint file of file type XDC. Copy the code from figure 1 and paste.
4. Run Synthesis.
5. Run Implementation and open Implemented Design.
6. Right-click Generate Bitstream and click Bitstream settings. Click 'Configure additional bitstream settings' and click the Startup tab. Change the Select Startup Clock dropdown to JTAGCLK and save settings.
7. Click Generate Bitstream.
8. Open Adept and connect Nexys4DDR and Initialize Chain.
9. Under the Config tab, click Browse on FPGA and navigate to the project location and upload the .bit file created from Generate Bitstream.
10. Click Program.

Part 2 - Hex Counter

1. Create a new project in Vivado.
2. Add the source file created in Part 1 and upload to project.
3. Create 2 new source files of file type VHDL and copy code from Section 2.2 and 2.3 in lab PDF, respectively.
4. Create a new constraint file of file type XDC. Copy the code from Figure 2 and paste.
5. Follow steps 4-10 from Part 1.