Simulation

After creating a project, you will need to create two source vhd files and insert the code located on the github page called:

• ha.vhdl
• ha_tb.vhdl

The half adder code has 2 inputs and 2 outputs.

• The inputs are a and b which take in numerical values.
• The outputs are s (sum) and c (carry).

The half adder test bench code creates the input values for a and b and calculates c and d,

Once you finish saving these files, hit the 'Run Simulation' in the flow navigator pane on the left hand side of the screen.

The graph shown to the right displays the time calculated for each input and output in the form on the wave in terms of ns. You will need to zoom in at the beginning of the graph to see these values.

After creating a project, you will need to create two source vhd files and insert the code located on the github page called:

• adder.vhdl
• adder_tb.vhdl

The full adder code improves the half adder code by adding another input variable for a total of:

• 3 input variables: i0, i1, cin (carry in)
• 2 output variables: s, co (carry out)

As a result of the addition input variable, a pattern array is used to store the truth table in the full adder test bench code.

Once you finish saving these files, hit the 'Run Simulation' in the flow navigator pane on the left hand side of the screen.

The graph shown to the right displays the time calculated for each input and output in the form on the wave in terms of ns. You will need to zoom in at the beginning of the graph to see these values.