PEOPLE
PROFESSOR
Rino Choi
Office: 5N333
Email: rino.choi@inha.ac.kr
Tel: +82-32-860-7525
Education
+ 9/1999~5/2004: Univ. of Texas at Austin, Texas - Ph.D. in Materials Science and Engineering
+ 3/1992~2/1994: Seoul National University, Korea - M.S. in Inorganic Materials Science and Engineering
+ 3/1988~2/1992: Seoul National University, Korea - B.S. in Inorganic Materials Science and Engineering
Professional Experience
9/07-Present: Inha University, Professor
M3D integration, low temperature anneals processes
CMOS scaling, Device reliability, Post-CMOS technology
Contributed to develop high performance reliable gate stack using high-k/metal gate
7/14 - 8/15: University of Texas at Dallas, Research Scientist
CMOS reliability
Worked with Professor Jiyoung Kim
1/11 - 2/14: KEIT, Program Director
R&D Planning for Semiconductor Process and Equipment Industry
1/04 - 8/07: SEMATECH, Project Engineer of ECR project
Managing 1 fellow, 3 engineers, and 3 internship
Developed novel reliability test methodologies for advanced gate stack devices
Rated ad a high performance project in 2 consecutive years by Program Advisory Group
Contributed to develop high performance reliable gate stack using high-k/metal gate
1/94 - 7/99: Daewoo Motor Company, Korea, Research engineer
Developed reliability test methodology to predict lifetime of car emission parts
Honors and Awards
2013 Best Poster Award in Korean Conference of Semiconductor (KCS2012)
2012 Best Poster Award in Korean Conference of Semiconductor (KCS2011)
2008 SSDM Paper Award in International Conference on Solid State Devices and Materials in Japan
2004 Sematech Corporate Excellence Award
2002 - 2003 University Continuing Fellowship
2001 Highlight session in VLSI Symposium in Kyoto
Research Interests and Technical Contributions
Process and device integration for future CMOS and memory application
Novel device structure and materials for post CMOS technologies and flat panel display applications
Novel device characterization methodology
Semiconductor device technology and reliability physics
Gate stack technology and reliability physics
Oxide semiconductor and dielectric for low temperature processes
Selected Publications
Low-Temperature Fabrication of High Quality Gate Insulator in Metal-Oxide-Semiconductor Capacitor Using Laser Annealing, IEEE Electron Device Letters, 40(2),8606421, pp. 167-170
Application of Single-Pulse Charge Pumping Method on Evaluation of Indium Gallium Zinc Oxide Thin-Film Transistors, IEEE Transactions on Electron Devices 65(9),8424088, pp. 3786-3790
Solution-Processed Rb-Doped Indium Zinc Oxide Thin-Film Transistors, IEEE Electron Device Letters 39(9),8433896, pp. 1330-1333
Low-Temperature Solution-Based In2O3 Channel Formation for Thin-Film Transistors Using a Visible Laser-Assisted Combustion Process, IEEE Electron Device Letters, 38(9),8000382, pp. 1259-1262
Others
8 Invited talks on device characterization and reliability in international conferences
Symposium organizer for IUMRS-ICEM2010
Guest editor for Microelectronic Engineering
Executive committee in International Symposium on Advanced Gate Stack Technology (2006-2008)
Senior Member in IEEE Electron Device Society