Research Area

The ASIC Lab (AI Semiconductor Integrated Circuit Laboratory) focuses on AI semiconductor circuit and system design, with particular emphasis on Compute-in-Memory (CIM)–based AI accelerators and computer architecture for efficient and intelligent computing systems.

Compute-in-Memory (CIM)–Based AI Accelerator Design

• • Exploration of CIM circuit and architecture using various memory technologies such as SRAM, eDRAM, and DRAM.

  • Developing memory-centric AI architectures that alleviate memory bottlenecks and improve energy efficiency.

Computer Architecture and System Design

• Designing on-chip memory hierarchies and interconnect structures to support high-bandwidth data communication.

• Integrating memory–compute co-design methodologies to achieve circuit–system performance balance in AI hardware.

Memory Circuit Design focuses on the development of high-speed and low-power circuits and operation schemes for various embedded and emerging memories, including SRAM, eDRAM, eMRAM, and RRAM. The research aims to design innovative circuit components and operation techniques that enable reliable, efficient memory systems, followed by chip fabrication and silicon verification.

Embedded Memory Circuit Design

• Design of high-speed, low-power memory (e. g. SRAM and eDRAM etc.) circuits for on-chip integration.

• Development of peripheral circuits and exploration of advanced read/write schemes for stability and access latency.

• Circuit-level noise margin and variation tolerance optimization for reliable embedded memory operation.
  
  

Emerging and Hybrid Memory Integration

• Circuit design for emerging non-volatile memories (e. g. MRAM and RRAM), targeting fast switching, low energy, and high endurance.

• Development of adaptive bias and voltage control techniques to ensure robust operation across process and temperature variations.

• Exploration of hybrid embedded memory architectures combining multiple memory technologies for data-centric computing.

Technology–Circuit Co-Design bridges semiconductor process technology and circuit design, enabling cross-layer optimization of power, performance, and reliability across logic, memory, and system ICs.

Device–Circuit Interaction and Co-Modeling

• Development of device–circuit co-simulation frameworks integrating TCAD and SPICE environments.

• Analysis of device parameter sensitivity (e.g., threshold voltage, leakage, parasitic effects) on circuit behavior.

• Creation of compact and Verilog-A models for emerging devices and memory structures.
  
  

Process-Aware and Memory-Oriented Circuit Design

• Design and modeling of process-aware and variation-tolerant circuits for advanced technology nodes.

• Exploration of 3D and hybrid integration co-design for high-density, high-efficiency semiconductor systems.