FIR filter in Verilog

Introduction

Our goal was to design a Finite Impulse Response (FIR) filter, where, N represents window length (5 in our test benches), x is the vector of input data, y is the vector of output data, and h is the vector of coefficients.

FSM design

There are 4 states in the FSM:

• s_reset: Reset the system on the asynchronous reset input
• s_coeff: Save the filter coefficients. The input coeff_enable is high
• s_error: Error state (eg less number of coefficients read in in s_coeff than expected or sample_enable and coeff_enable are high at the same time)
• s_sample: Read data samples and apply filtering. The input sample_enable is high

Synthesis

The expected synthesis results are shown below. The green parts are combinatorial and the blue parts are sequential

Code

The source code is available here