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About me
Academics
Professional Experience
Image Compression
DCT-based Image Compression
Fractal Compression
Motion Compensation
Image codec on Arduino
Image Processing
Point Transformations
Quantization & Dithering
Edges and Corners
Hough Transform
Quantization
Preprocessing for Edge Detection
Image Restoration
Mobile Image Scanner
Color spaces
Data Science
SOTU Analysis
Bill Speech Analysis
Sci-Hub Analysis
CelebA analysis using Spark
Deep Learning Frameworks
k-means case study
Kornia
Onnx optimizer
Computer Engineering
FIFO in Verilog
FIR filter in Verilog
About me
Academics
Professional Experience
Image Compression
DCT-based Image Compression
Fractal Compression
Motion Compensation
Image codec on Arduino
Image Processing
Point Transformations
Quantization & Dithering
Edges and Corners
Hough Transform
Quantization
Preprocessing for Edge Detection
Image Restoration
Mobile Image Scanner
Color spaces
Data Science
SOTU Analysis
Bill Speech Analysis
Sci-Hub Analysis
CelebA analysis using Spark
Deep Learning Frameworks
k-means case study
Kornia
Onnx optimizer
Computer Engineering
FIFO in Verilog
FIR filter in Verilog
More
About me
Academics
Professional Experience
Image Compression
DCT-based Image Compression
Fractal Compression
Motion Compensation
Image codec on Arduino
Image Processing
Point Transformations
Quantization & Dithering
Edges and Corners
Hough Transform
Quantization
Preprocessing for Edge Detection
Image Restoration
Mobile Image Scanner
Color spaces
Data Science
SOTU Analysis
Bill Speech Analysis
Sci-Hub Analysis
CelebA analysis using Spark
Deep Learning Frameworks
k-means case study
Kornia
Onnx optimizer
Computer Engineering
FIFO in Verilog
FIR filter in Verilog
Computer Engineering
This section documents some Computer Engineering/Software based projects
Image codec on Arduino
: A binary image codec using run length encoding on Arduino connected to a PC and an LCD
FIFO in Verilog
: A mixed clock FIFO design in Verilog
FIR filter in Verilog
: Implementation of a hardware FIR filter module in Verilog
Polynomial Evaluator in Verilog
: A handshake protocol based polynomial evaluation accelerator design in Verilog
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