FIFO in Verilog

Introduction and Specifications

The goal is to design a First In First Out (FIFO) buffer with parameterizable bit width and capacity. The FIFO should be mixed clock (that is separate clocks for read and write). The diagram below shows the input/output ports

read_clock (rising edge) + enqueue (level high): Store data from data_in
write_clock (rising edge) + dequeue (level high): Output data to data_out
full and empty are high if the FIFO is full or empty respectively
population shows the current number of contents in the FIFO
flush clears the FIFO

FSM design

The equations below show the FSM design for a FIFO of capacity 3. E and D refers to the enqueue and dequeue inputs respectively. For a FIFO with capacity c, there are c+2 states, where the 2 extra states correspond to empty and full FIFO.

Mealy Machine

Extended Mealy machine

Synthesis

The systhesis is shown schematically below. The green parts are combinatorial and the blue parts are sequential

Code

The source code is available here.

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