Figure 1:The inverter circuit
THE OUTPUT INTERCONNECT CAPACITANCE
We look at the output metal 1 pad as a capacitor, since there is a capacitance between the metal and the substrate below. We assume nothing else is under the metal pad. We assume a parallel plate model. The metal pad is 78 microns wide x 39 microns long. We assumed there is no fringing field capacitance, and that there is a double layer of oxide under the metal. We computed the capacitance of the metal pad as 105 ff.
The metal connecting the inverter to the output pad is 4755 microns long, and 4 lambda wide. We used the same parallel plate model as above. We assumed there is no fringing field capacitance, and that there is a double layer of oxide under the metal. We computed the capacitance of the metal interconnect from the diffusion-metal contacts to the output pad as 82.06 ff.
We assumed that Cd(n+p) ~ 12ff, and Cdinterconnect = 360ff. (You might get different answers if you compute these values).
THE OUTPUT CIRCUIT RESISTANCE
We computed the total resistance of the metal and n+ diffusion interconnect running from the inverter to the output pad. The n+ diffusion interconnect is 20 microns long, and 4 lambda wide. We assumed the metal sheet resistance is .06 ohms/square, and the diffusion resistance is 40 ohms/square. We ignored the p+ and n+ diffusion at the inverter. We assumed there is one contact total in the interconnect, since we are looking at fall time, so we ignore the contacts connecting p+ to the metal. Rdiffusion = 1600 ohms. Rmetal = 570 ohms. We considered the contact resistance at a typical value of 10 ohms/contact in our total.
We computed the channel resistance of the NMOS transistor in the linear region when Vin = 2.4v. Rchn = 422 ohms.
We neglected the output pad resistance.
DELAY/TIMING COMPUTATIONS
1. We decide to compare the speed of this circuit to one where the interconnection metal from the diffusion at the output of the inverter to the pad is made 8 lambda wide, instead of 4 lambda. Using the most accurate model you can, compare these two implementations for speed when the output is falling.
2. Repeat the comparison you did in Problem 1 assuming that you are only given the summary information that the total resistance in the output path is 2602 ohms, and the total capacitance is 559 ff in the original circuit. In the modified circuit, assume Rtot = 2317 ohms, and Ctot = 641ff .
3. Compute the fall time of the original inverter, ignoring wiring resistance, using the most accurate method you can.
4. Assume the original output metal interconnect is disconnected from the inverter and the output pad. Assume the resistance and capacitance values of the wires are lumped, just as we have given you. a) What is the fall time along this wire? b) What is the fall time with the wire width doubled?
5. Consider the original wire in Problem 4. Assume the wire resistance is .1178 ohms/micron. Assume the wire capacitance is .0172 ff/micron. Compute the fall time the most accurate way you can. Compare to your answer to problem 4a.
FRINGING FIELDS
6. Assume the output metal interconnect is subject to fringing fields. Use the curves shown in Fig. 6.18 to approximate the metal interconnect capacitance, including fringing fields, for the modified output metal interconnect 8 lambda wide. Reading C/Cpp off the figure is not easy so just approximate, noting that the y axis is a log scale. Points will not be deducted for inexact answers.
OTHER PROBLEMS
These problems are not related to the inverter example.
7. A 4-input NAND gate with unit size transistors drives three inverters with unit size transistors, through three parallel transmission gates with unit size devices. Assume Cg(n or p) = 90 ff, Rchn = 500 ohms, Rchp = 2000 ohms and Cd (drain or source) = 45 ff for the individual transistors. The 3 inverters are all attached at the outputs of the transmission gates. All three transmission gates are on, and we ignore any sharing of diffusion capacitances. Solve for the falling RC time constant at the output of the NAND gate and at the input to one of the inverters.
8. Use a chain of inverters to drive a 4 pf load. How many stages (n) are required in the inverter chain, assuming the first stage is an inverter with unit transistors, assuming equal delay in all stages, and assuming Cg(n+p) for the first inverter in the chain = 5 ff.? You can assume Cd(source or drain) = Cgn = Cgp. How much wider (a) are the transistors in each stage than the previous stage?
9. An inverter drives a long wire (9 mm) on a special kind of metal1 minimum width (3 lambda) to the input of another inverter. Both these inverters have identical unit size transistors. In order to speed up the circuit, Ernie's boss wants him to insert two inverters in the wire, so each wire segment is 3mm long. Ernie doesn't think he needs the inverters.
• Assume the capacitance of each 1 mm section of the wire is 50 ff. Assume the special kind of metal1 has resistance .025 ohms per square.
• Assume Cg(n or p) = 100 ff, Rchn = 250 ohms, Rchp = 1000 ohms and Cd (drain or source) = 40 ff for the original inverters.
• Use equivalent circuits and distributed RC time constants (Elmore delay) to show Ernie’s boss whether Ernie’s design is faster than the boss’s design or not.
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