EE477 - s08 hw6

Homework Assignment #6

Spring 2008 EE 477

Due April 21, 2008 11:59 PM, or in class/Den email April 22, 2008

Solutions will be posted evening of April 22

Worth 1.5 assignments

Each problem is worth 9 %, except problem 11 is worth 10%.

The first 5 problems in this assignment focus on an inverter and the interconnections to and from the inverter. The inverter input is on 8 lambda wide metal 2 for 9805 microns, then goes through a via and contact to reach poly, then on poly for 150 microns, including the gates. The poly is 2.4 times minimum width. The inverter output is on diffusion for 20 microns then goes through a contact to metal 1, and the metal 1 output goes to an output pad on the chip. The inverter is shown below. The gate of the NMOS transistor in the inverter is 3 times unit size width, and unit size channel length, and the gate of the PMOS transistor is 12 times unit size wide and unit size channel length. lambda is .125 microns. Assume Vdd is 2.5v. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .4 microns.

Figure 1:The inverter circuit

THE OUTPUT INTERCONNECT CAPACITANCE

The wire from the output of the inverter to the pad is on n+ then on the metal 1 layer. A short metal 1 strap connects p+ at the PMOS drain to the n+ diffusion. The output passes through 1 contact cut (diffusion-metal) at the output of the inverter from p+ to metal 1, one contact cut from metal 1 to n+ and 1 contact cut from n+ to metal 1.

1. We look at the output metal 1 pad as a capacitor, since there is a capacitance between the metal and the substrate below. We assume nothing else is under the metal pad. We assume a parallel plate model. Compute the capacitance of the metal pad. The metal pad is 78 microns wide x 39 microns long. For the oxide thickness, you will need to convert angstroms to microns. Assume there is no fringing field capacitance, and that there is a double layer of oxide under the metal.

2. The metal connecting the inverter to the output pad is 4755 microns long, and 4 lambda wide. Compute the capacitance of the metal interconnect from the diffusion-metal contacts to the output pad. Use the same parallel plate model as problem 1, above. Assume there is no fringing field capacitance, and that there is a double layer of oxide under the metal.

THE OUTPUT CIRCUIT RESISTANCE

3. Compute the total resistance of the metal and n+ diffusion interconnect running from the inverter to the output pad. The n+ diffusion interconnect is 20 microns long, and 4 lambda wide. Assume the metal sheet resistance is .06 ohms/square, and the diffusion resistance is 40 ohms/square. Include the contact resistance at a typical value of 10 ohms/contact in your total. Ignore the p+ and n+ diffusion at the inverter. Assume there is one contact total in the interconnect.

4. Compare the total output interconnect + contact resistance to the channel resistance of the NMOS transistor in the linear region when Vin = 2.4v. Can we neglect the output pad resistance?

FRINGING FIELDS

5. Assume the output metal interconnect is subject to fringing fields. Use the curves shown in Fig. 6.18 to approximate the metal interconnect capacitance, including fringing fields. Reading C/Cpp off the figure is not easy so just approximate, noting that the y axis is a log scale. Points will not be deducted for inexact answers.

DELAY COMPUTATIONS

6. Solve for the delay in seconds in a wire that is 600 microns long, if resistance is .025 ohms per .2 microns, and capacitance of the wire is .0015 ff per .2 microns. Show a portion of the distributed RC circuit.

7. Compare the distributed RC delay in problem 6 to the lumped RC delay, summing the R's and C's to get the lumped delay.

8. Solve for the output rising and falling RC time constants when a 3-input NAND gate with unit size transistors drives an inverter with unit size devices, through a transmission gate with unit size devices, assuming Cg(n or p) = 90 ff, Rchn = 500 ohms, Rchp = 1000 ohms and Cd (drain or source) = 45 ff for the individual transistors.

9. Use a chain of inverters to drive a 1 pf load. How many stages (n) are required in the inverter chain, assuming the first stage is an inverter with unit transistors, assuming equal delay in all stages, and assuming Cg(n+p) for the first inverter in the chain = 5 ff.? You can assume Cd(source or drain) = Cgn = Cgp. How much wider (a) are the transistors in each stage than the previous stage?

10. An inverter drives a long wire (0.9 mm) on a special kind of metal1 minimum width (3 lambda) to the input of another inverter. Both these inverters have identical unit size transistors. In order to speed up the circuit, Ernie's boss wants him to insert two inverters in the wire, so each wire segment is 0.3mm long. Ernie doesn't think he needs the inverter.

• Assume the capacitance of each .1 mm section of the wire is 5 ff. Assume the special kind of metal1 has resistance .025 ohms per square.

• Assume Cg(n or p) = 100 ff, Rchn = 250 ohms, Rchp = 1000 ohms and Cd (drain or source) = 40 ff for the original inverters.

• Use equivalent circuits and distributed RC time constants (Elmore delay) to show Ernie’s boss whether Ernie’s design is faster than the boss’s design or not.

11. Assume the interconnect resistance at the output of the inverter in problems 1-5 can be neglected. Assume Cdn (drain or source) = 40 ff for the inverter, and Cdp (drain or source) = 160 ff. Assume the input rises instantaneously. Compute the fall tme at the output of this inverter using the most accurate method you can. Make sure you compute C_L using the capacitances you found in problems 1 and 2 as well as any other capacitances.