2020-09-01
Went over class syllabus.
Overview of what equipment we will need.
2020-09-03
Discussed chapter 1-2 in the textbook.
Chapter 1 covered an introduction to VHDL.
Chapter 2 went over different VHDL statements.
2020-09-08
As a class we shared what states we are currently in.
A google sheet was made for who wants to borrow an FPGA.
Installation guide for GHDL on github.
Went over chapter 3: entity declaration in VHDL and IEEE standard libraries.
2020-09-10
Discussed chapter 4: VHDL Programming Paradigm.
Concurrent statements.
"<=" is the signal assignment operator; For example, A_out <= A_1 and A_2; The signal and operator were used to assign it to the output.
2020-09-15
Went over chapter 5 in the textbook.
Learned about process and sequential statements.
Also discussed data flow style architecture and behavioral style architecture.
2020-09-17
Created lab groups.
Reviewed VHDL operators.
2020-09-22
Chapter 8 Finite Machine Design Using WHDL.
Learned about types of FSM.
Moore-type: External output depends on state (not directly the input).
Went over coding for FSM.
GHDL examples: 4-to-1 multiplexer and 1-to-4 demultiplexer.
2020-09-24
Chapter 8 (one-hot coding), Gray code
Reviewed FSM (ex. looked at different outputs, states, bits, etc).
One-Hot Encoding for FSM: 1 bit, everything is zero.
Went over Gray Coding.
2020-09-29
Chapter 9, Semiconductor device fabrication .
Structural Modeling in VHDL.
Data-flow modeling, behavioral modeling, structural modeling.
2020-10-01
Chapter 10 Registers and Register Transfer Level.
Contributions and lab groups.
2020-10-06
Chapter 11, Electronic design automation (EDA).
2020-10-08
Chapters 12-13.
2020-10-13
No class, Monday schedule.
2020-10-15
Went over lab 1.
Showed us how to create a new Vivado project: "hexcounter".
Project type: RTL
Add sources -> add files -> leddec.srcs (code Professor already had).
Create files: "counter" and "hexcount".
Add Constraints: create "hexcount" file.
Go to boards, click on your board and the hit next.
2020-10-20
FPGA Lab 2 demo.
2020-10-22
FPGA Lab 3 demo.
Finished first 4 labs with Anthony.
2020-10-27
FPGA Lab Demos
2020-10-29
Updated some lab materials to website.
2020-11-03
Worked on website.
2020-11-05
Discussed with group on whether to do a final project or a final research paper.
2020-11-10
Finished lab 6 with group.
2020-11-12
Brainstormed final research paper ideas.
Updated some labs to the website.
2020-11-17
Decided on final project- Research Paper on "Autonomous Driving with FPGA"
2020-11-19
Researched scholarly articles for final project and created the outline.
2020-11-24
Worked on final project.
2020-11-26
Thanksgiving
2020-12-01
Worked on final project with group.
Added lab steps and results to site.
2020-12-03
Finished adding lab materials to site.
2020-12-08
Worked on final project with group.
Returned FPGA to Professor day before.
2020-12-10
Finished final project with group.