Using VHDL for Sequential Circuits

7.1 Simple Storage Elements Using VHDL

• The cross coupled cell forms what is referred to as a latch.
• The concept of a clocking signal is added to the device in order to enhance its controllability.
• Some type of pulse narrowing circuitry is added to the clocking signal to get to the flip-flop.
• The flip-flop is an edge-sensitive bit-storage device.

• The D flip-flop is best known for its ability to store (save, remember) a single bit.
• If the if condition is not met, the device does not change the value of Q and therefore it must remember the current value.
• The memory feature of the current value, or state, constitutes the famous bit storage quality of a flip-flop.
• If the input changes to an unspecified state, the output remains unchanged.

7.2 Inducing Memory: Data-flow vs. Behavioral Modeling

• Most sequential circuit design is about synchronizing events to a clock edge. Output changes only occur on a clock edge.
• Not explicitly specifying an output for every possible input condition generates a latch (a storage element).
• Although it would be possible to generate flip-flops using data-flow models, it wouldn't be explicitly clear as to what you are trying to achieve to people with a well-rounded knowledge of the subject of VHDL.

7.3 Important Points

• Storage elements in VHDL are induced by not specifying output conditions for every possible input condition.
• Unintended generation of storage elements is generally listed by the synthesizer as latch generation. Once again, latches are generated when there is an existing input condition to a circuit that does not have a corresponding output specification.
• Memory elements can be induced by both data-flow and behavioral models.
• If a signal declared in the entity declaration has a mode specifier of out, that signal cannot appear on the right-hand side of a signal assignment operator. This limitation is bypassed by using intermediate signals for any functional assignments and later assigning the intermediate signal to the output signal using a concurrent signal assignment statement.
• The mode specification of buffer should be avoided in favor of intermediate signals.