Chapter 5

Standard Models in VHDL Architectures

A data-flow style architecture specifies a circuit as a concurrent representation of the flow of data through the circuit.
Circuits are described by showing the input and output relationships between the various built-in components of the VHDL language.
If you exclusively used concurrent, conditional and selected signal assignment statement in your VHDL models, you have used a data-flow model.

You can see the flow of data within the circuit by examining the VHDL code.
It's easier to make an educated guess as to how the actual logic will appear when synthesizing the circuit.

Data-flow style works well for smaller circuits. However, when the circuits becomes more complex, it becomes more advantageous to use behavioral style.

The behavioral style architecture provides no details as to how the design is implemented in actual hardware.
VHDL code written in a behavioral style does not necessarily reflect how the circuit is implemented when it is synthesized. The behavioral style models how the circuit outputs will react to the circuit inputs.
Behavioral models provide you with various tools to describe how the circuit will behave and leave the implementation details up to the synthesis tool.
The heart of the behavioral style architecture is the process statement.

The process statement itself is a concurrent statement identified by its label, its sensitivity list, a declaration area, and a begin-end area containing instructions executed sequentially.
The main difference between the two architectures is the presence of the process statement in the listed code.
Below is an example of what a process statement looks like.

The execution of the sequential statements is initiated when a change in the signal contained in the process sensitivity list occurs.
Execution of statements within the process body continues until the end of the process body is reached.

The sequential style of a signal assignment statement is syntactically equivalent to the concurrent signal assignment statement.

The if statement is used to create a branch in the execution flow of the sequential statements.
Depending on the conditions listed in the body of the if statement, either the instructions associated with one or none of the branches is executed when the if statement is processed.

The if statement is a sequential statement found inside a process body while the conditional signal assignment statement is one form of concurrent signal assignment.

The case statement is somewhat similar to the if statement in that a sequence of statements is executed if an associated expression is true. The case statement differs from the if statement in that the resulting choice is made depending upon the value of the single control expression.

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