Chapter 3

VHDL Design Units

The VHDL entity construct provides a method to abstract the functionality of a circuit description to a higher level. It provides a simple wrapper for the lower-level circuitry. This wrapper effectively describes how the black box interfaces with the outside world.

The port_name_x is an identifier used to differentiate the various signals.

The next keyword (the keyword in) specifies the direction of the signal relative to the entity where signals can either enter, exit or do both. These input and output signals are associated with the keywords in, out and inout respectively.

The next keyword (the keyword std_logic) refers to the type of data that the port will handle. There are several data types available in VHDL but we will primarily deal with the std_logic type and derived versions.

*When you attempt to write fairly complicated VHDL code, you will need to split your code into different files, functions and packages constructors which will help you better deal with your code

Each port name is unique and has an associated mode and data type.
The VHDL compiler allows several port names to be included on a single line. Port names are separated by commas.
Port names are somewhat lined up in a feeble attempt to increase readability. Remember that white spaces are ignored by the compiler.
A comment, which tells us what this entity does, is included.
A black-box diagram of the circuit is also provided. Once again, drawing some type of diagram helps with any VHDL code that you may be writing.

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