Ladder Process

The Ladder Process

For the full history of Texas Instruments on this site please return to The Early History of Texas Instruments Semiconductors.

TI had to meet the huge demand for grown junction transistors that would arise as a result of the success of the TR-1 but existing manufacturing processes were too slow as Ed Millis recalls: “This was a very labour intensive process, and during the development of the Regency radio, it became apparent that this wasn't going to hack it, cost-wise, and TI needed a faster way to build the NPNs.”

That better method was developed by Elmer Wolff and became known as the ladder process. It provided a faster and more efficient manual method for assembling germanium bars into transistors. In addition, by using all corrosion resistant metals such as gold and platinum, the final clean-up etch could be done without the masking step necessary previously.

Rather than manually solder the bars directly to the transistor header large numbers of transistors were given all their terminations in a single step. Firstly the germanium bars were cut. “When they were dicing up the germanium crystals, they would slice it open and then do a light etch which would make the base junction visible. It looked like a line across the surface. They set up the saws to center that on the bar length.”

Using a graphite boat with a cut outs in the shape of a ladder the individual germanium NPN grown diffused bars (rungs of the ladder) were placed over thin die cut squares of a gold-germanium solder positioned at the end of each rung. This would solder them to the sides of the ladder (thin strips of platinum positioned below the rungs). The base connection was made by positioning an indium dot over the base of the transistor and tensioning a platinum

wire across the top of these. The boat was taken to an oven to fuse all these elements. “The indium dot was big enough to be somewhat forgiving on hitting the P layer.” This sped up the processing at the expense of performance: “The main problem was the indium dots in the ladder process caused a huge base-collector capacitance, which necessitated a neutralizing capacitor, custom-fitted, for each HF stage” according to Ed Millis. Even so “this process provided improved productivity at the time and was used at TI from 1954 to 1956 for some production” recalls its inventor. [Cornelison 1955 Millis 2011 Smithsonian Institute]

Cornelison B et al Materials and Methods of Manufacturing Solid State Devices US Patent 3076253 filed March 10^th 1955 Issued February 5^th 1963

Millis E 2011 Personal communications May 2011

Smithsonian Institute Accession 1987.0487.346 Transistor Ladder Assembly Display