This paper contains circuits designed to multiply two 8 bit binary numbers by Booth algorithm, array multiplication and unsigned binary multiplication algorithm. The circuits are designed using behavioral modeling in Verilog. The circuits were simulated with the help of Model Sim’s simulator for Verilog codes. The synthesis of the designed circuits was carried out with the help of Xilinx Integrated Software Environment 7.1 on Spartan 3(for array and unsigned multiplier) and cool runner 2 cpld(for booth multiplier) device.
Done by: Vikas Kashyap