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News:

• 12-05-2024: Added a like to Msys for a shell to develop Verilog code.

• 11-10-2024: Minor fixes to VcdView to fix net sorting in selection window and to properly destroy net selection window for create equation dialog (it was leaving extra windows laying around).  Also, sped up reload by not saving the existing nets in the copy buffer when cutting them before reloading and fixed bogus copy equation error when copying an expanded bus bit.

• 09-06-2024: Major upgrade to VcdView to fix a bunch of little annoying issues and added equations, fixed point and analog display. 

• 12-05-2023: Finally tracked down and fixed reload issue in VcdView when waves contain a Group.

• 10-26-2023: Added code to allow different sized displays to be used with Create Lcd Gui

CreateLcdGui.zip (V0.27 10-26-2023)

Windows based tool to design a graphical user interface for a touchscreen LCD display controlled by a low cost microcontroller.  Currently, a parallel or SPI 320x240 touchscreen named ELEGOO UNO R3 2.8 Inches TFT Touch Screen with SD Card Socket ($15) from Amazon or the SPI version are supported driven by Microchip 18F26K40 and dsPIC33EP512MC202 microcontrollers ($1.80 to $3.00).  Examples and schematics can be found on the PIC page.

The Raspberry Pi Pico is now supported as well which can be found on the Pico Page.

Instructions for use are included in the Help menu.

VcdView.zip (V1.06 11-10-2024)

Windows based Value Change Dump viewer that allows the results of a simulation to be analyzed.  This is great when teamed with Icarus, a fantastic free Verilog simulator and Msys / MinGw a nice Linux like shell and tools for Windows.  

New for 2024, added Verilog equations, fixed point display and analog wave display. The scroll wheel now will scroll the display up and down and the find next edge will scroll the display horizontally to center near the next edge if it is not in the current view.  A reload button has been added next to the VCD load icon to make reloading a simulation re-run easier.

Equations can be nested and will update dependent equations if a lower level equation is modified.  The equations are entered in standard Verilog format and also may contain built in functions that are listed below. 

• $EdgeCount(Signal,Reset)   Counts rising or falling edges of Signal

• $RiseEdgeCount(Signal,Reset) Counts rising edges of Signal

• $FallEdgeCount(Signal,Reset) Counts falling edges of Signal

• $SampleAndHold(Signal,Sample) Samples Signal when Sample is 1 and holds while Sample is 0

• $Delay(Signal,Amount) Returns the delayed Signal by Amount time units which can be positive or negative

• $Max(Signal0,Signal1,Signal2, ...) Returns the largest of the signals specified

• $Min(Signal0,Signal1,Signal2, ...) Returns the smallest of the signals specified

• $Avg(Signal0,Signal1,Signal2, ...) Returns the average of the signals specified

• $MinTotalSim(Signal) Returns the minimum value of the signal over the entire simulation

• $SignedMax(Signal0,Signal1,Signal2, ...) Returns the largest of the signed signals specified

• $SignedMin(Signal0,Signal1,Signal2, ...) Returns the smallest of the signed signals specified

• $SingedAvg(Signal0,Signal1,Signal2, ...) Returns the average of the signed signals specified

• $SignedMinTotalSim(Signal) Returns the minimum value of the signed signal over the entire simulation

• $SignedMaxTotalSim(Signal) Returns the maximum value of the signed signal over the entire simulation

• $RemoveX(Signal,StartTime,EndTime) Return a version of Signal without X or Zs only applied between StartTime and EndTime

NetList.zip (V0.04 9-17-2013)  Windows executable and source but just grab the two .cpp and the .h file and it will compile under Linux)

This is a little tool to convert Eagle CAD export of pin and part lists from a schematic to a Verilog netlist.  This is great when teamed with Icarus, a fantastic free Verilog simulator and Cygwin, a nice Linux like shell for Windows.  Download the zip file below if the link above does not work.