Address: Room 210, IIIT-Bangalore,26/C Electronics City, Hosur Road, Bangalore-560008
Phone: (080)-4140-7777 Extn. 159 (Office)
E-mail: subhajit_sen@iiitb.ac.in
Ph.D in Electrical Engineering, University of Waterloo, Waterloo,Ontario,Canada, 1997
Thesis Title: The Design of Sampling Mixer and A/D converter for High IF Digitization.
M.S. in Systems(Computer) Science from Louisiana State University, Baton Rouge, USA June 1991.
Thesis Title: “Triangulation Using Simulated Annealing algorithm”.
B.Tech in Electronics Engineering, Institute of Technology, Banaras Hindu University(IIT-Varanasi), Varanasi, India,December 1984.
projects related to power management & energy harvesting circuits for biomedical and WSN applications, wireless power telemetry and flexible electronics.
Since May 2009 I have been with Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT), Gandhinagar, Gujarat as Associate Professor. I have been teaching courses on Electronics and VLSI Design to B.Tech as well as M.Tech students, supervising B.Tech and M.Tech projects and thesis as well as personally conducting research on novel analog and mixed-signal circuit designs.
Courses taught:
EL-213 (Analog Circuits)
EL-422 (Analog CMOS Circuits)
EL-517 (Advanced Analog CMOS Circuits)
EL-424 (Labs in VLSI)
EL-512 (VLSI Subsystems)
EL-424(Topics in Medical Electronics)
B.Tech Thesis supervised:
(1) Design of an FPGA Based Audiometer
(2) Application of Adaptive Techniques for Noise cancellation
M.Tech Thesis supervised:
(1) Adaptive Analog Line Driver Using Digital Tuning
(2) Auto-tuning circuits for continuous-time filters
(3) Design and Layout of single-bit per stage pipelined ADC
Summer Research Internships supervised:
(1) ECG Amplifier
(2) Implementation of Genetic Algorithms
(3) Stepper Motor Controller with optical feedback
(4) MOSFET Device Simulation using PISCES
Have also mentored several teams of students for Texas Instruments- Analog Design Contest. Five student teams of DA-IICT have been short-listed for Phase-1A of TI Analog Design Contest 2011. The list of short-listed teams is available at http://www.uniti.in/analog-design-contest/analog-design-contest-2011/75 .
Sponsored Research Completed:
“Distortion and Accuracy Improvement in Sample-and-Hold Circuits for Analog-Digital Converters", Department of Science and Technology, Govt. of India (DST-NSERC grant no. SR/S3/EECE/0119/2010). The objective of the project is to develop high speed analog and mixed-signal circuits for analog-front-ends (AFE) used in advanced communication, networking and instrumentation systems. A novel bootstrapped-gate sample-and-hold circuit has been designed and layout implemented using 0.18 micron CMOS technology and submitted for fabrication.
“Novel Analog Circuits Using Double Gate MOSFET”, Indo-French Collaboration on Advanced Research (CEFIPRA). Department of Science and Technology, Govt. of India. The objective is to develop novel circuits using double-gate MOSFET in collaboration with ISEP, Paris, France.
VLSI Lab Development:
Have actively contributed to the development of VLSI Lab in terms of supervision and maintenance of Cadence analog as well as digital tools and their maintenance and the installation of PDK’s (process design kits): UMC 0.18 micron, AMS 0.35 micron, GPDK’s etc. Appropriate networking methodology was set up (NFS flow) and the previously existing Cadence installation and maintenance procedure was simplified to a great extent. A workshop on Cadence Design flow was organized in 2010.
Design of analog blocks and sub-systems for communication, audio, video and GPS related products :
SiRF Technologies, Bangalore (Nov. 2007-Jan. 2009):
Senior Principal Engineer with the RF/Mixed-signal division: My main contributions were to products related to GPS, multi-function radios (MFR) and power management:
a. Temperature Recorder: A temperature sensor and a sigma-delta ADC achieving 9-bit resolution was designed and implemented in 65nm/1.2V CMOS. Post-calibration temperature accuracy is < 0.1C over a temperature range of -50C to 110C. The intended application was temperature compensation of crystal oscillation frequency. Silicon characterization shows +/- 1 °C post-calibration accuracy.
b. Design of flash-ADC, DEM (DWA) logic and clock-generator for a 3rd order multi-bit continuous-time sigma-delta ADC in 65nm/1.2V CMOS for a digital FM radio receiver. Simulations and performance characterization of the ADC along with loop-filter. The analog blocks performed satisfactorily in the first silicon. The ADC achieved > 94 dB SNR. The RF chain was also analyzed for adjacent channel interference and receiver sensitivity. Performance gaps in the LNA and mixer specs were identified.
c. Design of a high accuracy band-gap voltage & current references in 65nm/1.2V CMOS. First silicon performed to the expected accuracy over supply voltage and temperature.
2. Cirrus Logic India Private Limited, Pune
(July 2001-Oct 2007).
VLSI architect/Project Manager. My responsibilities were in the design of blocks for PC audio and video, crystal oscillators and other general purpose blocks. I also contributed to substrate noise coupling and ESD related issues. The design centre was acquired by Sasken in April 2004:
a. Design and process migration of a 3rd order sigma-delta D/A converter and band-gap reference for PC audio products.
b. Design of a high-frequency (144.5 MHz) clock multiplication PLL for driving a DAC clock in a video encoder. This work involved investigation into sources of substrate-noise induced jitter in VCO’s and circuit techniques to reduce this jitter. Measurement results showed “good” quality of the video signal in the first-silicon.
c. Designed a crystal oscillator with both low-power/high-phase-noise and high-power/low-phase-noise modes: involved extensive negative-resistance & phase-noise characterization using Spectre-RF.
d. Re-designed a 10-bit SAR general purpose A/D converter and added a front-end amplifier and voltage reference targeted for 90 nm/1.2V CMOS. Layout supervision.
3. Cypress Semiconductor India(formerly Arcus Technology Pvt. Limited, India), Bangalore : Jan. 1998–Jan. 2000:
Engineering Project Manager : My job responsibilities Design of mixed-signal integrated circuit blocks for DWDM optical interfaces, defense electronics and LVDS:
(a) Physical interface of a WDM(Wavelength Division Multiplexing) system with SERDES: includes VCSEL(laser) transmitter, TIA(Trans-impedance Amplifier), transmit and receive PLL’s.
(b) LVDS receiver for Sharp Corp., Japan: includes LVDS buffer, PLL and framing logic. LVDS buffer operating at 490 Mb/s and PLL resolution of 11 picoseconds. My contributions were in the PLL architecture specification, technical negotiations with the customer and technical guidance. The silicon was tested successfully and found to be working to specifications.
(c) 4-bit 1.25 GSamples/s A/D and D/A converter with 300 Mb/s data I/O for a high-speed RF application. The customer was an Indian defense lab. The chip was tested and found to be operational in the system at > 500 MSamples/s.
5. Semiconductor Complex Limited,Chandigarh : October 1984 – July 1988
Senior Design Engineer: My Job responsibilities: to develop analog CMOS LSI integrated circuits. I worked in a team which was involved in the development and characterization of analog building-block cells.
6. Space Applications Center, , ISRO, Ahmedabad : (June-August 1983): Designed and successfully tested an Adaptive Delta-Modulator for video signals as summer trainee.
PAPERS REVIEWED:
Journals: Have reviewed:
(1) A paper on RF CMOS circuit design for IEEE Transactions on CAS-II in April 2011.
(2) A paper for IEEE Transactions on Circuits & Systems-I in analog CMOS circuit design in 2006.
(3) A paper for IEEE Journal of Solid-State Circuits bandpass sigma-delta modulator for RF demodulation in 2005.
Conferences: Have reviewed:
(1) A few papers on analog CMOS circuit design for International Symposium on Electronic System Design (ISED) for the years 2011 & 2012 (http://ised.seedsnet.org/).
(2) A few papers on analog CMOS circuit design for IEEE Int’l Conf. On VLSI Design for 2007.
WORKSHOPS/SEMINARS ETC. ORGANIZED:
(1) Organized a talk by Prof. A. N. Chandorkar of IIT-Bombay on MOS Modeling for weak-inversion/sub-threshold operation at Sasken Communications, Bangalore in 2000. The intent was to explore the feasibility of weak-inversion for channel-decoding (Viterbi etc.) using analog circuits.
(2) Organized a talk by Prof. Bharadwaj Amrutur of IISc Bangalore on Adaptive Techniques to Reduce Power in Digital Circuits on 14th October 2011.
MISCELLANEOUS ACTIVITIES:
Visited Univ. of Cambridge between October 26th and November 6th 2015, CAPE group (under Electrical Engg. Dept.) hosted by Prof. Gehan Amaratunga and Arokia Nathan.
Visited Univ. of Cambridge in March 2014 for discussions on research into flexible electronics with Prof. Gehan Amaratunga, Florin Udrea, Bill Milne, Hennig Sirringhaus, Mark Welland.
Visited ISEP, Paris on 7th May 2014 for discussions on collaborative research with Prof. Amara, Costen Anghel, Andrei Vladimirescu, Thomas Ea.
Consulted on biomedical instrumentation with Dr. Ryan Cooper of Redmed, Bangalore.
Delivered an Institute Lecture on “The Art & Science of VLSI Chip Design: Bridging the Analog and Digital World” on Sept. 16th 2012.
Chaired a session on Analog circuit design at VDAT-2011, Pune
Visited MindTree, Pune on 8th July 2011. This group has developed India’s first Bluetooth RF front-end chip.
Co-Examiner for Ph.D student at Dharamsingh Desai Instt. Of Technology, Nadiad, Gujarat in 2011, 2012 and 2013.
Attended INUP (Indian Nanotechnology Users Program) Workshop at IIT-Bombay in Dec. 2010.
Reviewed and examined several M. Tech theses on parameter extraction using non-linear optimization techniques and a thesis on FinFET design for Microelectronics group of IIT-Bombay in 2006 and 2007.
Gave a talk on Charge-Pump design for low reference spur PLL at a seminar for Microelectronics group of IIT-Bombay in 2007.
Served on the recruitment panel for lab assistants for DAIICT labs in April 2011.
Attended a few IEEE Distinguished colloquia organized at IISc-Bangalore:
Fabless IC Design Challenges by Dr. Rakesh Kumar (Sept. 2011)
Wireless SOC design by Dr. David Su and on Sensor design by Dr. Kofi Makinwa (2009)
MEMBERSHIPS:
(1) Senior Member of IEEE & IEEE Solid-State Circuits Society.