List of Publications

Journal Publications

1. Subhajit Sen, “Analysis of Tracking Distortion in Bootstrapped gate MOSFET Sample-Hold Circuits and a Method for its Minimization”, IETE Journal of Research, Jan-Feb 2011.

2. W. Yu, S. Sen, B. Leung, “ Distortion Analysis of Sampling Mixer Using Time-varying Volterra series”, IEEE Transactions on Circuits and Systems-II, January 1999.

3. S. Sen, B.Leung, "A Class-AB High-speed Low-power Opamp in BiCMOS Technology", IEEE Journal of Solid-State Circuits,,September 1996, Vol. 31, No. 9,pp. 1325-1330.

4. Chinmaye Ramamurthy, Chetan D. Parikh and Subhajit Sen, “Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches,” Circuits, Systems, and Signal Processing, Online February 2021.(doi: https://doi.org/10.1007/s00034-021-01652-6)

5. Chinmaye Ramamurthy, Chetan D. Parikh and Subhajit Sen, "A Deterministic Digital Calibration Technique for Pipelined ADCs using a Non-nested Algorithm", Analog Integrated Circuits and Signal Processing, Springer, 2021.

Conference/Workshop Publication

1. Anshuman Mahapatra, Chetan D Parikh and Subhajit Sen, "A 10 uA All CMOS Current Reference Circuit with PVT Compensation Using Digital Programming", 35th International Conference on VLSI Design and 2022, 21st International Conference on Embedded Systems (VLSID), Feb-26th - Mar-2nd 2022.

2. Chinmaye Ramamurthy, Chetan D Parikh and Subhajit Sen, "Digital Calibration of 1.5 bits/stage Algorithmic ADC", ISOCC-2021, 18th International SOC Design Conference, South Korea, 6 - 9 October 2021

3. Sounak Das, Subhajit Sen, "A Multi-phase LC-Ring-Based Voltage Controlled Oscillator", ISED-2021, Gandhinagar,

4. Chinmaye Ramamurthy, Chetan D Parikh and Subhajit Sen, “Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients,” in 34th International Conference on VLSI Design and 2021 20th International Conference on VLSI Design & Embedded Systems (VLSID), Guwahati; India, February 20-24, 2021, pp. 29-34. (doi: https://doi.org/10.1109/VLSID51830.2021.00010)

5. Uma Kulkarni, Chetan Parikh, Subhajit Sen, “A systematic approach to determining the weights of capacitors in the DAC of a non-binary redundant SAR ADC”, IEEE International Conference on VLSI Design, Jan. 2018, Pune.

6. Mahesh Zanwar, Subhajit Sen, "Programmable Output Multi-phase Switched-Capacitor Step-up DC-DC Converter with SAR-based Regulation", IEEE International Conference on VLSI Design, Jan. 2017.

7. Mahesh Zanwar, Subhajit Sen, "Programmable CMOS Step-Up DC-DC Converter", 2016 IEEE ICSEE Conference, Eilat, Israel, Nov. 17th 2016

8. Mahesh Zanwar, Subhajit Sen, "Switch selection & sizing in CMOS implementation of variable output switched capacitor step-down DC-DC converter", 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, Dec. 2015

9. Mahesh Zanwar, Subhajit Sen, "Design of Multiphase Binary and Fibonacci Switched Capacitor Step-down DC-DC Converter for Energy Harvesting Applications", Advances in Energy Conversion Technologies, Jan. 28-30, 2016, Manipal.

10. Mahesh Zanwar, Subhajit Sen, "Design of CMOS Programmable Output Binary and Fibonacci Switched Capacitor Step-down DC-DC Converter", IEEE International Conference on VLSI Systems, Architectures, Technology, Applications, (IEEE VLSI-SATA), January 10-12 2016, Bangalore.

11. Sowmya Narayanswamy, N. Oraon, Subhajit Sen, Madhav Rao, “Development of 3D Shadow Mask using 3D Printer”, IEEE CONECCT, July 10-11 2015, Bangalore.

12. Gowthami Prasanna Banda, Subhajit Sen, “A Low Voltage Cascode Biasing Circuit with Gain-Boosting”, IEEE CONECCT, July 10-11 2015, Bangalore.

13. Subhajit Sen, "Programmable Switched-Capacitor DC-DC Converters", Workshop on Modeling, Simulation and Computational Techniques(WMSC), Jaipur,16th Jan.2015.

14. Subhajit Sen, K.A.Shaik, J. Mukherji, P. Dhalvaniya, “A Distortion Reduction Technique, for Bootstrapped-Gate MOS Sample-and-Hold Circuits Using Body Effect Compensation”, IEEE-FTFC (Low-Voltage-Low-Power) Conference, May 6^th 2014, Monte-Carlo, Monaco. (S. France).

15. V.R.Bhumireddy, K.A.Shaik, A.Amara, Subhajit Sen, Chetan Parikh, D.Nagchoudhuri, A.Ioinovici, “Design of Low Power and High Speed Comparator with sub-32-nm Double Gate MOSFET”, IEEE International Conference On Circuits And Systems (ICCAS), 18^th – 19^th 2012 Sept., Kuala Lumpur, Malaysia.

16. S. Sen, “MOSFET Modeling and Parameter Extraction for Low Distortion Analog Circuits Operating in Triode region”, MOS-AK/GSA India 2012, International Workshop on Device Modeling For Microsystems, March 18^th 2012, New Delhi.

17. Subhajit Sen, Noshir Dubash, Dan Babitch, “A Compact Temperature Recorder at 1.8μA/Hz Conversion rate and 1.1 °C accuracy for SOCs”, IEEE International Conference on VLSI Design, Jan. 2012.

18. Subhajit Sen, A. Hadji-Abdolhamid, “A Low Glitch Current Switch with Reduced Swing and Its Application to PLL Charge Pump”, VLSI Design and Test Symposium (VDAT-2011), Pune, July 8^th 2011.

19. Sen, Subhajit., Leung B., “A 150 MHz 13-bit 12.5 mW IF Digitizer Using Sampling Mixer”, IEEE Custom Integrated Circuits Conference, Santa Clara, USA, May 1998.

20. Subhajit Sen, B.Leung, "A Low Power BiCMOS Opamp Using "Pseudo PNP" transistors" , IEEE International Symposium on Circuits and Systems (ISCAS), Chicago, May 1993.

21. Subhajit Sen, B.Leung, “Low Power BiCMOS Opamp”, IEEE Bipolar Circuits & Technology Meeting (BCTM), Minneapolis, May, 1995.

22. Subhajit Sen, S.Q. Zheng, "Triangulation of a Point Set Using Simulated Annealing" ACM/SIGAPP Symposium on Applied Computing, March 1992, Kansas.

23. Subhajit Sen, R. Doddamani, “Design of High Speed Load Adaptive CMOS Digital Output Buffers”, VLSI Systems, Design and Technology Conference, December, 2000, IIT-Mumbai.

Tutorials Presented

1. Subhajit Sen, Chetan Parikh, “Design of Hearing Aids”, VLSI Design and Test Symposium (VDAT-2013), Jaipur, July 27^th – 30^th 2013, Jaipur.

2. Subhajit Sen, Chetan Parikh and Dipankar Nagchoudhuri, “Fundamentals & Design of Phase-Locked Loops (PLLs)”, VLSI Design and Test Symposium (VDAT-2011), Pune, July 7^th 2011.

Technical Memo: (Internal Technical Memo, Cirrus Logic): The Logical Effort Method and its Mixed-signal applications.

PATENTS

(1) US Patent No. 6,323,734: “Trans-impedance Amplifier”, Cypress Semiconductor.

(2) US Patent No. 7,053,684 : “ Reduced jitter charge pumps and circuits and systems utilizing the same”, Cirrus Logic.

Awards