Research(Building)

Low Power Group

Parallel Programming Group

Design Reliability Enhancement Group

Clock Optimization Group

Retention Flip-flop Group

System Design and Verification Group

Integrated Circuit Stress Group

  The complexity of verifying a System on Chip (SoC) increases dramatically because of integration of heterogeneous components and complicated interactions between components. Therefore, this group present methodology and algorithm to verify critical bugs caused by interactions at system level.

  Integrated circuit stress group is solving the problem of thermal-mechanical in stacking dies. Through Silicon Via (TSV) is used for passing signal, power and even reducing thermal affection in stacking dies. However TSV in interposer with full copper leads stress, and this stress may cause deforming  even cracking of dies. This group is developing several approaches to relief this phenomenon.

Thermal Analysis Group