A Logic Gate performs a boolean operation on one or more binary inputs and produces a single binary output. In NMOS, a logic gate is created with a single depletion mode Pull Up transistor and one or more enhancement mode Pull Down transistors that are arranged in a Pull Down Network.
A Pull Down Network is described by Wikipedia as a "network of parallel and/or series circuits, such that if the desired output for a certain combination of boolean input values is zero (or false), the PDN will be active, meaning that at least one transistor is allowing a current path between the negative supply and the output. This causes a voltage drop over the load, and thus a low voltage at the output, representing the zero. (see NMOS logic)".
The simplest examples of pull-down networks that we see in the 6561 die shot are:
Inverter: A single pull-down transistor.
2-input NAND gate: Two pull-down transistors in series.
2-input NOR gate: Two pull down transistors in parallel.
Other examples of more complex pull-down networks include:
3 or more input NAND gate
3 or more input NOR gate
AND gate
OR gate
Inverting super buffer
Non-inverting super buffer
2-1 AND-OR-INVERT
2-2 AND-OR-INVERT
2-2 OR-AND-INVERT
On the sub-pages below, we'll look for examples of each of these logic gates in 6561 die shot.