Pull Down

The Pull Down transistor is the second type of enhancement mode transistor that exists in the 6561. They exist predominantly as part of a logic gate of some kind. The simple case is the Inverter (discussed in a later section), where there is a single Pull Down transistor below the depletion mode Pull Up transistor.

A logic gate can be a lot more complex than this though. For a single Pull Up depletion mode transistor, there can be multiple Pull Down transistors below the Pull Up that are arranged in what is known as a Pull Down Network. The simplest examples of logic gates with multiple Pull Down transistors are the NAND and NOR gates (which we will cover in a later section). For an NMOS logic gate, the enhancement mode transistors below the output of the gate (which is also the source of the Pull Up) are what form the Pull Down Network for that gate.

The following image shows five pull down transistors labelled:

Also labelled are the VDD and VSS metal to diffusion contacts. Identifying VDD and VSS goes a long way towards working out where the pull down transistors are, and also in telling the difference between a pull down and a pass transistor. If a transistor is immediately above VSS (which is GND) then it has to be a pull down transistor.

We can also work it out through a process of elimination. In the image above, there are four depletion mode Pull Up transistors. These are easily recognisable as the fatter more rectangular shaped polysilicon areas that are very close to VDD (which is +5V). There are also two Pass Transistors in the image above. These are the short transistors where the gate is connected to the unlabelled metal to polysilicon contacts. In general, a pass transistor is shorter than a pull down transistor, so this can be used to distinguish between the two types of enhancement mode transistor.