Pull Up

The NMOS inverter is the basic circuit that shows the main features we need to understand to work out the logic of the 6561 chip. An inverter requires a pull up device of some kind. A resistive line could be used, but this would take up far too much of the chip's surface to be practical. There are also a couple of ways that an enhancement mode MOS transistor could be used for the pull up, and these approaches were used in early NMOS processes. For example, a saturated enhancement mode transistor (one that is always on) can be used as a pull up, but its pull up speed (rising transient) was much slower relative to its power consumption when pulled down. This wasn't ideal. There were other approaches that required an additional voltage source, which likewise wasn't ideal.

The early enhancement mode pull up mechanisms were discarded in favour of the Depletion Mode transistor. It overcomes the pull up speed issue of the saturated enhancement mode transistor and doesn't require an additional voltage. An ion implantation step is used during fabrication to make some of the transistors in to depletion mode transistors. This results in the threshold being less than zero, which means that at zero gate-source voltage, the depletion mode transistor is ON. When a depletion mode transistor is used as a pull up device, its gate is connected to its source, which means that it is always turned on. This form of logic family was called Depletion-mode NMOS logic. This is the type of pull up used in NMOS fabrication at the time that the 6561 was made.

For any logic gate formed using Depletion-mode NMOS logic, there will be a single depletion mode pull up transistor that is placed between VSS and the logic gate's output, and as already noted, its gate will usually be connected to its source (there are situations where this doesn't directly happen, such as when used in a Super Buffer, but that will be discussed under more advanced topics). So this means we'll usually find a depletion mode transistor quite close to VSS, and we should see its gate (being polysilicon) connected to its source (being diffusion), i.e. we will usually see a polysilicon to diffusion contact (also known as a buried contact).

Depletion mode transistors are usually several times longer than the enhancement mode transistors used in the same logic gate. This is in order to achieve the proper inverter threshold logic. This is perhaps our greatest tip with regards to finding depletion mode transistors in the 6561 die shot.

As already mentioned, an ion implantation step is used during fabrication when creating a depletion mode transistor. Unfortunately this ion implantation is almost impossible to see.

Given all the above, our best tips for spotting a depletion mode pull up transistor are:

• • It is longer than a normal enhancement mode pull down or pass transistor.

  • It has a buried contact between its gate and source.

  • It's drain is in close proximity to VDD.

The following image shows six depletion mode transistors:

Three of them are not under metal and are therefore easier to spot. One of those is shown in the image below:

The metal line and metal to diffusion contact are for VDD. The diffusion connected to VDD passes under the long polysilicon rectangle and thus forms a transistor. This longer polysilicon gate (longer from the perspective of the diffusion) is typical of a depletion mode transistor. Also clearly visible in the above example is the buried contact between the polysilicon gate and the diffusion source. This is at the top. The image below labels these to make it clearer: