ARM

VFP - Vector Floating Point Operations

• • VFPv1 - obsoleted by ARM

  • VFPv2 - optional on ARMv5 and ARMv6 cores

    • • Supports standard FPU arithmetic (add, sub, neg, mul, div), full square root

      • 16 64-bit FPU registers

  • VFPv3[-D32]

    • • Broadly compatible with VFPv2 but adds

        • • Exception-less FPU usage

          • 32 64-bit FPU registers as standard

          • Adds VCVT instructions to convert between scalar, float and double.

          • Adds immediate mode to VMOV such that constants can be loaded into FPU registers

  • VFPv3-D16

    • • As above, but only has 16 64-bit FPU registers in VFPv3-D16 variant

  • VFPv3-F16 variant

    • • Uncommon but supports IEEE754-2008 half-precision (16-bit) floating point

  • VFPv4

    • • Cortex-A5

      • Has a "fused multiply-accumulate"

Instruction Set : http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf

Details on GCC floating-point options

For historical reasons and to match the ARM RVCT kit, the GCC FPU and ABI selection options are not entirely orthogonal. The -mfloat-abi= option controls both the ABI, and whether floating point instructions may be used. The available options are:

• • soft: Full software floating point.

  • softfp: Use the FPU, but remain compatible with soft-float code.

  • hard: Full hardware floating point.

In addition, the -mfpu= option can be used to select a VFP/NEON (or FPA or Maverick) variant. This has no effect when -mfloat-abi=soft is specified.

The combination of -mfpu=vfp and -mfloat-abi=hard is not available in FSF GCC 4.4; see TODO section below for options.

See /VfpComparison for an in depth discussion and some performance research.