1-D one-dimensional
2-D two-dimensional
3-D three-dimensional
ALU arithmetic and logic unit
AMP asymmetric multiprocessing system
API application program interface
ASA acyclic sequential algorithm
ASIC application-specific integrated circuit
ASMP asymmetric multiprocessor
CAD computer-aided design
CFD computational fluid dynamics
CMP chip multiprocessor
CORDIC coordinate rotation digital computer
CPI clock cycles per instruction
CPU central processing unit
CRC cyclic redundancy check
CT computerized tomography
CUDA compute unified device architecture
DAG directed acyclic graph
DBMS database management system
DCG directed cyclic graph
DFT discrete Fourier transform
DG directed graph
DHT discrete Hilbert transform
DRAM dynamic random access memory
DSP digital signal processing
FBMA full-search block matching algorithm
FDM finite difference method
FDM frequency division multiplexing
FFT fast Fourier transform
FIR finite impulse response
FLOPS floating point operations per second
FPGA field-programmable gate array
GF(2m) Galois field with 2m elements
GFLOPS giga floating point operations per second
GPGPU general purpose graphics processor unit
GPU graphics processing unit
HCORDIC high-performance coordinate rotation digital computer
HDL hardware description language
HDTV high-definition TV
HRCT high-resolution computerized tomography
HTM hardware-based transactional memory
IA iterative algorithm
IDHT inverse discrete Hilbert transform
IEEE Institute of Electrical and Electronic Engineers
IIR infinite impulse response
ILP instruction-level parallelism
I/O input/output
IP intellectual property modules
IP Internet protocol
IR instruction register
ISA instruction set architecture
JVM Java virtual machine
LAN local area network
LCA linear cellular automaton
LFSR linear feedback shift register
LHS left-hand side
LSB least-significant bit
MAC medium access control
MAC multiply/accumulate
MCAPI Multicore Communications Management API
MIMD multiple instruction multiple data
MIMO multiple-input multiple-output
MIN multistage interconnection networks
MISD multiple instruction single data stream
MIMD multiple instruction multiple data
MPI message passing interface
MRAPI Multicore Resource Management API
MRI magnetic resonance imaging
MSB most significant bit
MTAPI Multicore Task Management API
NIST National Institute for Standards and Technology
NoC network-on-chip
NSPA nonserial–parallel algorithm
NUMA nonuniform memory access
NVCC NVIDIA C compiler
OFDM orthogonal frequency division multiplexing
OFDMA orthogonal frequency division multiple access
OS operating system
P2P peer-to-peer
PA processor array
PE processing element
PRAM parallel random access machine
QoS quality of service
RAID redundant array of inexpensive disks
RAM random access memory
RAW read after write
RHS right-hand side
RIA regular iterative algorithm
RTL register transfer language
SE switching element
SF switch fabric
SFG signal flow graph
SIMD single instruction multiple data stream
SIMP single instruction multiple program
SISD single instruction single data stream
SLA service-level agreement
SM streaming multiprocessor
SMP symmetric multiprocessor
SMT simultaneous multithreading
SoC system-on-chip
SOR successive over-relaxation
SP streaming processor
SPA serial–parallel algorithm
SPMD single program multiple data stream
SRAM static random access memory
STM software-based transactional memory
TCP transfer control protocol
TFLOPS tera floating point operations per second
TLP thread-level parallelism
TM transactional memory
UMA uniform memory access
VHDL very high-speed integrated circuit hardware description language
VHSIC very high-speed integrated circuit
VIQ virtual input queuing
VLIW very long instruction word
VLSI very large-scale integration
VOQ virtual output queuing
VRQ virtual routing/virtual queuing
WAN wide area network
WAR write after read
WAW write after write
WiFi wireless fidelity