Siacoin chip (blake2b)

Common details for the crypto mining chips:

• • the chips have a common (inter-chip) networking infrastructure, featuring automatic neighbors discovery, DHCP-like automatic address assignment, message routing, automatic root node election

  • the chips can be connected in large networks (100's of chips)

  • the chips are designed to be connected (each) to 4 neighbors, one of which can be a main controller (eg. an FPGA)

  • the network of chips can be connected to the main controller in multiple points, for redundancy

  • the Bitcoin, Siacoin and Dogecoin chips feature a configurable size of the coinbase & merkle-tree buffers

  • the chips have a configurable number of redundant hashing cores and coinbase hashers and merkle-tree hashers, and feature an automated self-test upon startup that checks the correct functioning of the previous hashers, their buffers and the main hashing cores, and are able to disable the faulty parts and run with the valid ones (if at all possible)

  • full software simulation test implemented

  • Bitcoin, Dogecoin, Siacoin, Kadena and CKB chip prototypes have been implemented on Xilinx Zynq-Ultrascale+ ZCU104 FPGA (Handshake is too large for the available FPGA, and Ergo can't be implemented on FPGAs)

A project analysis for the manufacturing of crypto mining machines (for commercial sales & mining) can be found here 12-07-2022--Project-analysis.pdf (previous versions 06-07-2022--Project-analysis.pdf, 25-06-2022--Project-analysis.pdf)

No source code is provided for these chips. For further information about these chips or for business ideas, please contact me here: ghazi.bousselmi@gmail.com or info@tachchouri-shop.nl

Here are some estimated characteristics for the Siacoin chip: