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For gate "Width" the transistor grow in the Y dimension
1, 2, 3 and 4 unit widths of the same length transistor
This picture depicts 4 transistors of the same "Length" and 4 multiples of a unit "Width" from N=1 to N=4 where N is the number of units. 
The transistor on the far left is a 1 unit width, next over is 2 unit width, next over is 3 unit width and the far right transistor is 4 unit width. 

The path resistance can be thought of exactly like physical resistors and  A two unit size device will have one half the "On Resistance" of a one unit device but twice the parasitic input capacitance. Two Transistors in Series will have to be twice as wide (2 units) to have the same On Resistance as a single device. 

Now lets see if we can make it more clear (or totally confuse you). NMOS Drain current in "Saturation" is linearly related to the "width" of the device as: 
Drain Current Equation when Vds > Vgs - Vt... 
That's one heck of an equation... The thing I failed to grasp as a student was the difference between "process parameters" and "design parameters"
"Process parameters" are things that are determined by a given process technology node (I.e. 180nm, 65nm, 16nm, etc...) and you can't do anything about
"Design parameters" are things that you, as a designer, have control over. 

For now standard Fabless IC design in a commercial process (TSMC, IBM, Global Foundries, etc...) the only parameters a designer has control over are W, L, Vgs and Vds.
For CMOS digital circuits, Vgs is almost always equal to the supply (except during switching) and the supply is also determined by the chosen process node.

So the hooks to control Id, and thus the on resistance, is the ratio of Width to Length. Everything else is pre-determined. 
Most of the time when making digital gates you want to use the minimum length to minimize area so then the only thing you are really controlling is the individual transistor widths.
With Digital Gates the Gate Voltage is either 0 or "1"=Vsupply (except during transitions) and the source voltage (Vs) is connected to ground either directly or through another device. This directly determines that Vg - Vs = Vgs = 1 - 0 = 1. Furthermore when the assumption that a CMOS gate always drives another CMOS gate holds true the drain will be pulled to ground after the parasitic capacitance of the load has been discharged. With the drain pulled to ground this means that Vd= 0 so Vds = 0-0. 

Checking the transistor operating region: Vgs = 1, Vds = 0 so Vgs > Vt (the device is "on") but Vds < Vgs - Vt (All "on" digital devices operate in the triode region)
NMOS Drain Current in the Triode Region
This second drain current equation is the "triode region" one that is more applicable during switching conditions
The "Width" of the transistor linearly affects the drain current regardless of which equation and voltage conditions used. This means that a device with 4*W will have 4 times the current as a 1*W device under the same Vgs and Vds (Voltage) conditions. Now, if the transistor is able to drive 4 times more current under the same voltage conditions, V=IR holds up so: V/(N*I)  = R and the effective "on resistance" of a device linearly decreases with additional width.

The capacitive load assumption is true for all digital synthesized designs and true enough in mixed signal land b/c the designer should know when they have selected to drive a resistive load and then it becomes a matter of output impedance vs load impedance.