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There are plenty of sites about cmos fabrication.
There are plenty of sites about circuit design.
There is not a whole lot of information about the considerations for actually designing integrated circuit layout... By this, I mean my first several Google search page returned poor results related to international copyright laws and people offering paid courses.
I learned this stuff at NCSU in ECE546 layout tutorial and have been doing mixed signal ic design in industry for several years.
Lets start with the most basic digital logic gate of them all, the cmos digital inverter:
The circuit workings of an inverter can be found ad nauseam, but basically, the PMOS (top device) turns on when A is low(equal to vss) and the NMOS(bottom symbol) turns on when A is high(equal to vdd). CMOS logic gates all act in this manner and fully switch high and low when settled. The transients of the switching are determined by the parasitic(stuff like resistance, capacitance and inductance, that must physically exist) loading on A and the "on resistance" of the device driving A. The on resistance is determined by the transistor current equation and the capacitance by device and layout geometry which is what we are discussing.
There are two views that are shown when people talk about layouts: top view and cross sectional (and they significantly confused me as a student in my first transistor course).
The top view of an inverter layout looks, something, like this:
I say "something like" b/c while functional, that's not a very good layout in terms of interconnect-ability and scaling...
The cross sectional view of an inverter looks something like this:
This view is if you were to cut a silicon wafer physically through the top view of the inverter and look at it sideways... but unfortunately it's not one to one for the picture from the top view to the cross section because the well contacts are different...
Confused yet? Well, I was when I was first encountering this material.
The cross sectional view ONLY shows the "Length" of the transistor, which as a student in the first class I couldn't understand how that was possibly the length since pictorially it's clearly the width of the transistor in the cross sectional image...
Imagine if you could hold an NMOS transistor section in your hand...
The yellow region represents the p-type substrate
The Red Regions represent the source and drain N-type doping
The orange represents the poly gate
between the orange and yellow there is actually a,difficult to see, tiny purple region depicting the gate oxide
The blue is the contact metalization
and the green is the nitride layer over the gate.
Changing to a similar but not identical model...
The gate "Length" is the cross sectional view image width
In this particular model the "Gate Length" would be roughly 1mm
For gate "Width" the transistor grow in the Y dimension
This picture depicts 4 transistors of the same "Length" and 4 multiples of a unit "Width" from N=1 to N=4 where N is the number of units.
The transistor on the far left is a 1 unit width, next over is 2 unit width, next over is 3 unit width and the far right transistor is 4 unit width.
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