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There is a register within the processor that has a variety of flags that it can use to signal the results from various operations. We will consider the following registers.
The carry flag is used to indicate when an arithmetic carry or borrow has been generated out of the MSB after an arithmetic operation.
The zero flag is used to check the result of an arithmetic operation. It is set to 1, or true, if an arithmetic result is zero, and reset (to 0) otherwise.
The sign flag used to indicate whether the result of the last mathematical operation resulted in a negative or positive number. Is set to the value of the MSB (the left hand bit).
Overflow flag is set if a result is too large a positive number or too small a negative number (excluding sign-bit) to fit in a register, cleared otherwise.
An overflow occurs when the computer attempts to handle a number that is too large for it.
Every computer has a range of values that it can represent.
If during execution of a program it arrives at a number outside this range, it will experience an overflow error.
In computer processors, the overflow flag is usually a single bit register used to indicate when an arithmetic overflow has occurred in an operation.
We will calculate the value stored in an 8 bit register as a result of adding the 8-bit two’s complement numbers 1111 0001 (-15) and 0000 0111. (+7).
There is no carry or overflow so these flags are not set. The result is not zero so the zero flag is not set and the result is not 0 so the zero flag is cleared.
We will calculate the value stored in an 8 bit register as a result of adding the 8-bit two’s complement numbers 0111 1111 (+127) and 0000 0111 (+7).
(127 + 7= 134) 0 1000 0110. The sign bit is simply a copy of the MSB which in this case is 1. As the addition involved two positive numbers (sign 0) and the result has a negative sign (sign bit 1) then this cannot be a valid result so the overflow flag is set to 1.
We will calculate the value stored in an 8 bit register as a result of adding the 8-bit two’s complement numbers 1110 1000 and 0001 1000.
The carry bit is set to 1 as there was a carry out of the addition. A positive and negative number can result in a positive result so there has been no overflow so the overflow flag is not set. But as the number is zero then the zero flag is set to 1. This can be important to help avoid divide by zero errors.
State the value stored in an 8 bit register as a result of adding the 8-bit two’s complement numbers 1110 0111 + 0110 0011 (-25 + 99) = 74 (0100 1010)
The only flag that is set is the carry flag due to there being a carry out of the operation.