After removing the heatsink we can see the Core i5-8300H die mounted face down on the package substrate.

The connectivity between the CPU and the 2 SODIMM sockets was determined as shown below. Connections to DIMM A, the socket closest to the CPU are shown in black. while those to DIMM B farthest from the CPU are shown in red. Individual bytes are grouped together on either side of the central area providing address and control signals. Unconnected pins between byte 3 and the address and control section are likely reserved for the parity byte which would only be used in servers with x72 DIMMs. DM/DBI signals are not provided by the Core i5-8300H. These inputs to the SODIMMs are tied to Vdd.

DDR4 memory channel signals were observed using a Tektronix TLA7012 logic analyzer with a TLA7BB4 acquisition module. Although the module is capable of 50GHz asynchronous sampling, a 12.5GHz sampling rate provided sufficient timing resolution for DDR4 traffic. A Nexus Technology NEX-SO4INTR260-HS passive interposer was placed between DIMM A socket and the 8GB memory module to provide signals to the logic analyzer.

On power-up the Core i5-8300H writes the DDR4 mode registers and adjusts timing through a long sequence of read and write operations. Many of the new features introduced with DDR4 are not used. The error checking command/address parity or write data CRC features are not enabled, nor is command address latency. The ODT pin is inactive during operation. Instead, the Core i5-8300H employs dynamic ODT with timing controlled by read and write commands using Rttpark=Rzq/7 and Rttwr=Rzq/3.